參數(shù)資料
型號(hào): PI7C8150AMAE
廠商: Pericom
文件頁(yè)數(shù): 96/111頁(yè)
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 208-FQFP
標(biāo)準(zhǔn)包裝: 24
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-FQFP(28x28)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 85 of 111
APRIL 2006 – Revision 1.1
14.1.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
Function
Type
Description
31:0
I/O Limit
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit top address of an address range
for the bridge to determine when to forward I/O transactions from
one interface to the other.
Reset to 0
14.1.25
ECP POINTER REGISTER – OFFSET 34h
Bit
Function
Type
Description
7:0
Enhanced
Capabilities Port
Pointer
R/O
Enhanced capabilities port offset pointer. Read as DCh to indicate
that the first item resides at that configuration offset.
14.1.26
INTERRUPT LINE REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
7:0
Interrupt Line
R/W
For POST to program to FFh, indicating that the PI7C8150A does not
implement an interrupt pin.
14.1.27
INTERRUPT PIN REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
15:8
Interrupt Pin
R/O
Interrupt pin not supported on the PI7C8150A
14.1.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
Bit
Function
Type
Description
16
Parity Error
Response
R/W
Controls the bridge’s response to parity errors on the secondary
interface.
0: ignore address and data parity errors on the secondary interface
1: enable parity error reporting and detection on the secondary
interface
Reset to 0
17
S_SERR_L
enable
R/W
Controls the forwarding of S_SERR_L to the primary interface.
0: disable the forwarding of S_SERR_L to primary interface
1: enable the forwarding of S_SERR_L to primary interface
Reset to 0
06-0057
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