- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11744 > PI7C8150AMAE (Pericom)IC PCI-PCI BRIDGE 2PORT 208-FQFP PDF資料下載
參數(shù)資料
| 型號： | PI7C8150AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 74/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 208-FQFP |
| 標準包裝： | 24 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-FQFP（28x28） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁當前第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 65 of 111
APRIL 2006 – Revision 1.1
Memory Write induces master abort
When PI7C8150A receives a target abort or a master abort in response to the delayed
locked read transaction, this status is passed back to the initiator, and no locks are
established on either the target or the initiator bus. PI7C8150A resumes forwarding
unlocked transactions in both directions.
7.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
PI7C8150A ignores upstream lock and transactions. PI7C8150A will pass these
transactions as normal transactions without lock established.
7.3
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, PI7C8150A must
maintain the lock on the target bus for any subsequent locked transactions until the initiator
relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a
locked sequence. On subsequent transactions in the sequence,
the target retry has no effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock.
PI7C8150A does not know whether the current transaction is the last one in a sequence of
locked transactions until the initiator de-asserts the LOCK_L signal at
end of the transaction.
When the last locked transaction is a delayed transaction, PI7C8150A has already
completed the transaction on the target bus. In this example, as soon as PI7C8150A detects
that the initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state
while FRAME_L is de-asserted, PI7C8150A de-asserts the LOCK_L signal on the target
bus as soon as possible. Because of this behavior, LOCK_L may not be de-asserted until
several cycles after the last locked transaction has been completed on the target bus. As
soon as PI7C8150A has de-asserted LOCK_L to indicate the end of a sequence of locked
transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C8150A de-asserts
LOCK_L on the target bus at the end of the transaction because the lock was relinquished
at the end of the write transaction on the initiator bus.
When PI7C8150A receives a target abort or a master abort in response to a locked delayed
transaction, PI7C8150A returns a target abort or a master abort when the initiator repeats
the locked transaction. The initiator must then de-assert LOCK_L at the end of the
transaction. PI7C8150A sets the appropriate status bits, flagging the abnormal target
termination condition (see Section 3.8). Normal forwarding of unlocked posted and
delayed transactions is resumed.
When PI7C8150A receives a target abort or a master abort in response to a locked posted
write transaction, PI7C8150A cannot pass back that status to the initiator. PI7C8150A
asserts SERR_L on the initiator bus when a target abort or a master abort is received during
06-0057
相關PDF資料 |
PDF描述 |
|---|---|
| PIC18F2515-I/SP | IC MCU FLASH 24KX16 28-DIP |
| V300A15E500B2 | CONVERTER MOD DC/DC 15V 500W |
| PIC16C73B-04I/SO | IC MCU OTP 4KX14 A/D PWM 28SOIC |
| GRM1555C1H301JA01D | CAP CER 300PF 50V 5% NP0 0402 |
| PIC16LF876A-I/ML | IC PIC MCU FLASH 8KX14 28QFN |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150AMAE-33 | 功能描述:外圍驅動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AND | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE |
| PI7C8150AND-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-TO-PCI BRIDGE 256BGA - Rail/Tube |
| PI7C8150ANDE | 功能描述:外圍驅動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
發(fā)布緊急采購，3分鐘左右您將得到回復。