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參數(shù)資料
| 型號： | PI7C8150AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 60/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 208-FQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-FQFP（28x28） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 52 of 111
APRIL 2006 – Revision 1.1
PI7C8150A does not have a hardware mechanism to guarantee data synchronization for
posted write transactions. Therefore, all posted write transactions must be followed by a
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
6
ERROR HANDLING
PI7C8150A checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C8150A always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C8150A
always attempts to be transparent when reporting errors, but this is not always possible,
given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8150A implements the following:
PERR_L and SERR_L signals on both the primary and secondary interfaces
Primary status and secondary status registers
The device-specific P_SERR_L event disable register
This chapter provides detailed information about how PI7C8150A handles errors.
It also describes error status reporting and error operation disabling.
6.1
ADDRESS PARITY ERRORS
PI7C8150A checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C8150A detects an address parity error on the primary interface,
the following events occur:
If the parity error response bit is set in the command register, PI7C8150A does not
claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally
and accepts the transaction if it is directed to or across PI7C8150A.
PI7C8150A sets the detected parity error bit in the status register.
PI7C8150A asserts P_SERR_L and sets signaled system error bit in the status register,
if both the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the command register.
When PI7C8150A detects an address parity error on the secondary interface, the following
events occur:
06-0057
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150AMAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AND | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE |
| PI7C8150AND-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-TO-PCI BRIDGE 256BGA - Rail/Tube |
| PI7C8150ANDE | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
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