參數資料
型號： PI7C8150AMAE
廠商： Pericom
文件頁數： 50/111頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 208-FQFP
標準包裝： 24
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-FQFP（28x28）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 43 of 111
APRIL 2006 – Revision 1.1
with their appropriate values before setting either the I/O enable bit or the master enable bit
in the command register in configuration space.
4.2.2
ISA MODE
PI7C8150A supports ISA mode by providing an ISA enable bit in the bridge control
register in configuration space. ISA mode modifies the response of PI7C8150A inside the
I/O address range in order to support mapping of I/O space in the presence of an ISA bus in
the system. This bit only affects the response of PI7C8150A when the transaction falls
inside the address range defined by the I/O base and limit address registers, and only when
this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h).
When the ISA enable bit is set, PI7C8150A does not forward downstream any I/O
transactions addressing the top 768 bytes of each aligned 1KB block. Only those
transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and
limit I/O address range are forwarded downstream. Transactions above the 64KB I/O
address boundary are forwarded as defined by the address range defined by the I/O base
and limit registers.
Accordingly, if the ISA enable bit is set, PI7C8150A forwards upstream those I/O
transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB
of I/O space. The master enable bit in the command configuration register must also be set
to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are
forwarded upstream only if they fall outside the I/O address range.
When the ISA enable bit is set, devices downstream of PI7C8150A can have I/O space
mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere
in I/O space above the 64KB boundary.
4.3
MEMORY ADDRESS DECODING
PI7C8150A has three mechanisms for defining memory address ranges for forwarding of
memory transactions:
Memory-mapped I/O base and limit address registers
Prefetchable memory base and limit address registers
VGA mode
This section describes the first two mechanisms. Section 4.4.1 describes VGA mode. To
enable downstream forwarding of memory transactions, the memory enable bit must be set
in the command register in configuration space. To enable upstream forwarding of memory
transactions, the master-enable bit must be set in the command register. The master-enable
bit also allows upstream forwarding of I/O transactions if it is set.
CAUTION
If any configuration state affecting memory transaction forwarding is changed by a
configuration write operation on the primary bus at the same time that memory
transactions are ongoing on the secondary bus, response to the secondary bus memory
06-0057
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參數描述
PI7C8150AMAE-33 功能描述:外圍驅動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150AND 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE
PI7C8150AND-33 制造商:Pericom Semiconductor Corporation 功能描述:PCI-TO-PCI BRIDGE 256BGA - Rail/Tube
PI7C8150ANDE 功能描述:外圍驅動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
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