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參數(shù)資料
| 型號： | PI7C8150AMAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 94/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 208-FQFP |
| 標準包裝： | 24 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-FQFP（28x28） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 83 of 111
APRIL 2006 – Revision 1.1
Bit
Function
Type
Description
29
Received Master
Abort
R/WC
Set to 1 (by a master) when transactions on its secondary interface
are terminated with Master Abort
Reset to 0
30
Received System
Error
R/WC
Set to 1 when S_SERR_L is asserted
Reset to 0
31
Detected Parity
Error
R/WC
Set to 1 when address or data parity error is detected on the
secondary interface
Reset to 0
14.1.17
MEMORY BASE REGISTER – OFFSET 20h
Bit
Function
Type
Description
3:0
R/O
Lower four bits of register are read only and return 0.
Reset to 0
15:4
Memory Base
Address [15:4]
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be 0.
Reset to 0
14.1.18
MEMORY LIMIT REGISTER – OFFSET 20h
Bit
Function
Type
Description
19:16
R/O
Lower four bits of register are read only and return 0.
Reset to 0
31:20
Memory Limit
Address [31:20]
R/W
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one interface
to the other. The upper 12 bits correspond to address bits [31:20]
and are writable. The lower 20 bits corresponding to address bits
[19:0] are assumed to be FFFFFh.
14.1.19
PEFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
Bit
Function
Type
Description
3:0
64-bit addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
15:4
Prefetchable
Memory Base
Address [31:20]
R/W
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
06-0057
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150AMAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AND | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE |
| PI7C8150AND-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-TO-PCI BRIDGE 256BGA - Rail/Tube |
| PI7C8150ANDE | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
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