參數(shù)資料
型號(hào)： PDI1394P25BY
廠商： NXP SEMICONDUCTORS
元件分類： 網(wǎng)絡(luò)接口
英文描述： 1-port 400 Mbps physical layer interface
中文描述： DATACOM, INTERFACE CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 39/42頁(yè)
文件大?。?/td> 214K
代理商： PDI1394P25BY
Philips Semiconductors
Product data
PDI1394P25BY
1-port 400 Mbps physical layer interface
2002 Oct 11
39
T
CLK_ACTIVATE
CTL0
LPS
SV01815
ISO
SYSCLK
D0 – D7
LREQ
(high)
(c)
7 cycles
(b)
CTL1
(a)
Figure 25.
Interface Initialization, ISO High
The sequence of events for initialization of the PHY-LLC interface
when the interface is in the non-differentiated mode of operation
(ISO terminal is high) is as follows:
1. LPS reasserted. After the interface has been in the reset or
disabled state for at least the minimum T
RESTORE
time, the LLC
causes the interface to be initialized and restored to normal
operation by reasserting the LPS signal. (In the above diagram,
the interface is shown in the disabled state with SYSCLK low
inactive. However, the interface initialization sequence described
here is also executed if the interface is merely reset but not yet
disabled.)
2. SYSCLK activated. If the interface is disabled, the PHY
re-activates its SYSCLK output when it detects that LPS has
been reasserted. SYSCLK will be restored within 60 ns. The
SYSCLK output is a 50% duty cycle square wave with a
frequency of 49.152 MHz +100 ppm (period of 20.345 ns).
During the first seven cycles of SYSCLK, the PHY continues to
drive the CTL and D terminals low. The LLC is also required to
drive its CTL and D outputs low for one of the first six cycles of
SYSCLK but to otherwise place its CTL and D outputs in a
high-impedance state. The LLC continues to drive its LREQ
output low during this time.
3. Receive indicated. Upon the eighth SYSCLK cycle following
reassertion of LPS, the PHY asserts the Receive state on the
CTL lines and the data-on indication (all ones) on the D lines for
one or more cycles.
4. Initialization complete. The PHY asserts the Idle state on the
CTL lines and logic 0 on the D lines. This indicates that the
PHY-LLC interface initialization is complete and normal operation
may commence. The PHY will now accept requests from the
LLC via the LREQ line.
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