參數(shù)資料
型號： PDI1394P25BY
廠商： NXP SEMICONDUCTORS
元件分類： 網(wǎng)絡(luò)接口
英文描述： 1-port 400 Mbps physical layer interface
中文描述： DATACOM, INTERFACE CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 33/42頁
文件大?。?/td> 214K
代理商： PDI1394P25BY
Philips Semiconductors
Product data
PDI1394P25BY
1-port 400 Mbps physical layer interface
2002 Oct 11
33
18.5
The LLC controls the state of the PHY-LLC interface using the LPS
signal. The interface may be placed into a reset state, a disabled
state, or be made to initialize and then return to normal operation.
When the interface is not operational (whether reset, disabled, or in
the process of initialization) the PHY cancels any outstanding bus
request or register read request, and ignores any requests made via
the LREQ line. Additionally, any status information generated by the
PHY will not be queued and will not cause a status transfer upon
restoration of the interface to normal operation.
Interface reset and disable
The LPS signal may be either a level signal or a pulsed signal,
depending upon whether the PHY–LLC interface is a direct
connection or is made across an isolation barrier. When an isolation
barrier exists between the PHY and LLC (whether of the Philips
bus-holder type or Annex J type) the LPS signal must be pulsed. In
a direct connection, the LPS signal may be either a pulsed or a level
signal. Timing parameters for the LPS signal are given in Table 20.
The LLC requests that the interface be reset by deasserting the LPS
signal and terminating all bus and request activity. When the PHY
observes that LPS has been deasserted for T
LPS_RESET
, it resets
the interface. When the interface is in the reset state, the PHY sets
its CTL and D outputs in the logic 0 state and ignores any activity on
the LREQ signal. The timing for interface reset is shown in Figure 20
and Figure 21.
Table 20. LPS Timing Parameters
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
T
LPSL
T
LPSH
LPS low time (when pulsed) (see Note 1)
0.09
2.60
μ
S
LPS high time (when pulsed) (see Note 1)
0.021
2.60
μ
S
LPS duty cycle (when pulsed) (see Note 2)
20
55
%
T
LPS_RESET
T
LPS_DISABLE
T
RESTORE
T
CLK_ACTIVATE
Time for PHY to recognize LPS deasserted and reset the interface
2.60
2.68
μ
S
Time for PHY to recognize LPS deasserted and disable the interface
26.03
26.11
23
3
μ
S
Time to permit optional isolation circuits to restore during an interface reset
15
μ
S
Time for SYSCLK to be activated from reassertion of LPS
—
60
nS
NOTES:
1. The specified T
LPSL
and T
LPSH
times are worst–case values appropriate for operation with the PDI1394P25. These values are broader than
those specified for the same parameters in the P1394a Supplement (i.e., an implementation of LPS that meets the requirements of P1394a
will operate correctly with the PDI1394P25).
2. A pulsed LPS signal must have a duty cycle (ratio of T
LPSH
to cycle period) in the specified range to ensure proper operation when using an
isolation barrier on the LPS signal (e.g., as shown in Figure 8)
3. The maximum value for T
RESTORE
does not apply when the PHY–LLC interface is disabled, in which case an indefinite time may elapse
before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is
deasserted for less than T
LPS_DISABLE
.
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