參數(shù)資料
型號: PDI1394P25BY
廠商: NXP SEMICONDUCTORS
元件分類: 網(wǎng)絡(luò)接口
英文描述: 1-port 400 Mbps physical layer interface
中文描述: DATACOM, INTERFACE CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù): 12/42頁
文件大?。?/td> 214K
代理商: PDI1394P25BY
Philips Semiconductors
Product data
PDI1394P25BY
1-port 400 Mbps physical layer interface
2002 Oct 11
12
13.0
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITION
LIMITS
UNIT
MIN
TYP
68
MAX
R
Θ
jA
Junction-to-free-air thermal resistance
Board mounted, no air flow
°
C/W
14.0
AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmit jitter
TPA, TPB
0.15
ns
Transmit skew
Between TPA and TPB
0.10
ns
t
r
t
f
TPA, TPB differential output voltage rise time
10% to 90%; At 1394 connector
0.5
1.2
ns
TPA, TPB differential output voltage fall time
90% to 10%; At 1394 connector
0.5
1.2
ns
t
SU
t
H
t
D
Set-up time, CTL0, CTL1, D0–D7, LREQ to SYSCLK
50% to 50%; See Figure 2
5
ns
Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK
50% to 50%; See Figure 2
0
ns
Delay time SYSCLK to CTL0, CTL1, D0–D7
50% to 50%; See Figure 3
0.5
11
ns
C
L
Capacitance load value CTL0, CTL1, D0–D7,
SYSCLK
Input capacitance CTL0, CTL1, D0–D7, LREQ
10
pF
C
i
3.3
pF
15.0
TIMING WAVEFORMS
SV01098
56
TPAn+
TPBn+
TPAn–
TPBn–
Figure 1.
Test load diagram
SV01099
t
SU
t
H
SYSCLK
Dn, CTLn, LREQ
Figure 2.
Dn, CTLn, LREQ input set-up and hold times
SV01803
t
D
SYSCLK
Dn, CTLn
Figure 3.
Dn, CTLn, output delay relative to SYSCLK
相關(guān)PDF資料
PDF描述
PDI20AC1H0R
PDI20AC1H0X
PDI20AC1HR0
PDI20AC1HRX
PDI20AC1L0R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394P25EC 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface
PDI-15R 制造商:Power Dynamics Inc 功能描述:
PDI-15RH-5 制造商:Power Dynamics Inc 功能描述:
PDI-15RH-5-R-G30 制造商:Power Dynamics Inc 功能描述:PDI Series 15 Position Right Angle Socket High Density D-Sub
PDI-15S 制造商:POWER DYNAMICS 功能描述: 制造商:Power Dynamics Inc 功能描述: