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參數(shù)資料
| 型號(hào)： | PDI1394P25BY |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 1-port 400 Mbps physical layer interface |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁(yè)數(shù)： | 30/42頁(yè) |
| 文件大?。?/td> | 214K |
| 代理商： | PDI1394P25BY |
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Philips Semiconductors
Product data
PDI1394P25BY
1-port 400 Mbps physical layer interface
2002 Oct 11
30
The sequence of events for a null packet reception is as follows:
Receive operation initiated. The PHY indicates a receive
operation by asserting receive on the CTL lines. Normally, the
interface is idle when receive is asserted. However, the receive
operation may interrupt a status transfer operation that is in
progress so that the CTL lines may change from status to receive
without an intervening idle.
Data-on indication. The PHY asserts the data-on indication code
on the D lines for one or more cycles.
Receive operation terminated. The PHY terminates the receive
operation by asserting Idle on the CTL lines. The PHY shall assert
at least one cycle of Idle following a receive operation.
SYSCLK
(a)
(b)
CTL0, CTL1
D0–D7
XX
00
00
10
00
01
FF (“data-on”)
SV01761
(c)
Figure 17.
Null Packet Reception Timing
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