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參數(shù)資料
| 型號： | PDI1394P25BY |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 1-port 400 Mbps physical layer interface |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 38/42頁 |
| 文件大?。?/td> | 214K |
| 代理商： | PDI1394P25BY |
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Philips Semiconductors
Product data
PDI1394P25BY
1-port 400 Mbps physical layer interface
2002 Oct 11
38
T
CLK_ACTIVATE
CTL0
LPS
SV01814
ISO
SYSCLK
D0 – D7
LREQ
(low)
(c)
7 cycles
5 ns. min
10 ns. max
(d)
(b)
CTL1
(a)
Figure 24.
Interface Initialization, ISO Low
The sequence of events for initialization of the PHY-LLC interface
when the interface is in the differentiated mode of operation (ISO
terminal is low) is as follows:
1. LPS reasserted. After the interface has been in the reset or
disabled state for at least the minimum T
RESTORE
time, the LLC
causes the interface to be initialized and restored to normal
operation by re-activating the LPS signal. (In the above diagram,
the interface is shown in the disabled state with SYSCLK
high-impedance inactive. However, the interface initialization
sequence described here is also executed if the interface is
merely reset but not yet disabled.)
2. SYSCLK activated. If the interface is disabled, the PHY
re-activates its SYSCLK output when it detects that LPS has
been reasserted. SYSCLK will be restored within 60 ns. The
PHY commences SYSCLK activity by driving the SYSCLK output
low for half a cycle. Thereafter, the SYSCLK output is a 50%
duty cycle square wave with a frequency of 49.152 MHz +100
ppm (period of 20.345 ns). Upon the first full cycle of SYSCLK,
the PHY drives the CTL and D terminals low for one cycle. The
LLC is also required to drive its CTL, D, and LREQ outputs low
during one of the first six cycles of SYSCLK (in the above
diagram, this is shown as occurring in the first SYSCLK cycle).
3. Receive indicated. Upon the eighth SYSCLK cycle following
reassertion of LPS, the PHY asserts the Receive state on the
CTL lines and the data-on indication (all ones) on the D lines for
one or more cycles (because the interface is in the differentiated
mode of operation, the CTL and D lines will be in the
high-impedance state after the first cycle).
4. Initialization complete. The PHY asserts the Idle state on the
CTL lines and logic 0 on the D lines. This indicates that the
PHY-LLC interface initialization is complete and normal operation
may commence. The PHY will now accept requests from the
LLC via the LREQ line.
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