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參數(shù)資料
| 型號： | PDI1394P25BY |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 1-port 400 Mbps physical layer interface |
| 中文描述： | DATACOM, INTERFACE CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48 |
| 文件頁數(shù)： | 11/42頁 |
| 文件大?。?/td> | 214K |
| 代理商： | PDI1394P25BY |
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Philips Semiconductors
Product data
PDI1394P25BY
1-port 400 Mbps physical layer interface
2002 Oct 11
11
12.0
OTHER DEVICE I/O
SYMBOL
PARAMETER
TEST CONDITION
MIN
—
TYP
56
MAX
—
UNIT
mA
See Note 1
I
DD
Supply current
See Note 2
—
40
—
mA
See Note 3
—
38
—
mA
μ
A
I
DD–PD
Supply current in power down mode
PD = V
DD
in power down mode
390 k
resistor between cable power
and CPS pin: Measured at cable power
side of resistor
—
150
—
V
TH
Cable power status threshold voltage
4.7
—
7.5
V
Hi h l
High-level output voltage, pins CTL0,
CTL1, D0–D7, SYSCLK
CTL1, D0 D7, SYSCLK
V
DD
>= 2.7 V, I
OH
= –4 mA, ISO = V
DD
V
DD
>= 3.0 V, I
OH
= –4 mA, ISO = V
DD
Annex J: I
OH
= –9 mA, ISO = 0
I
OL
= 4 mA, ISO = V
DD
Annex J: I
OL
= 9 mA, ISO = 0
V
DD
= 2.7 V, I
OH
= –4 mA; See Note 4
V
DD
>= 3.0 V, I
OH
= –4 mA; See Note 4
V
DD
= 2.7 V, I
OL
= 4 mA; See Note 4
2.4
—
—
V
V
OH
2.8
—
—
V
V
DD
–0.4
—
—
—
V
V
OL
Low-level output voltag ,
CTL1, D0–D7, SYSCLK
—
0.4
V
,
—
—
0.4
V
V
OH
High level output voltage pin C/LKON
High-level output voltage, pin C/LKON
2.4
—
—
V
2.7
—
—
V
V
OL
Low-level output voltage, pin C/LKON
—
—
0.3
V
I
BH+
Positive peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
Negative peak bus holder current, pins
CTL0, CTL1, D0–D7, LREQ
Input current, pins LREQ, LPS, PD,
TEST0, BRIDGE, PC0–PC2
Off-state current, pins CTL0, CTL1,
D0–D7, C/LKON
Pullup current, RESET input
ISO = V
DD
, V
I
= 0 V to V
DD
0.05
—
1.0
mA
I
BH–
ISO = V
DD
, V
I
= 0 V to V
DD
–1.0
—
–0.05
mA
I
I
ISO = 0 V; V
DD
= 3.6 V
—
—
5
μ
A
I
OZ
V
O
= V
DD
or 0 V
–5
—
5
μ
A
I
RST-UP
I
RST-DN
V
I
= 1.5 V or 0 V
V
I
= V
DD
, PD = V
DD
–90
—
–20
μ
A
mA
Pulldown current, RESET input
.4
1.6
2.8
V
IT+
Positive going threshold voltage,
LREQ, CTL0, CTL1, D0–D7, C/LKON
inputs
ISO = 0 V
V
DD
/2 + 0.3
—
V
DD
/2 + 0.9
V
V
IT–
Negative going threshold voltage, LREQ,
CTL0, CTL1, D0–D7, C/LKON inputs
Positive going threshold voltage, LPS
inputs
Negative going threshold voltage, LPS
inputs
TPBIAS output voltage
ISO = 0 V
V
DD
/2 – 0.9
—
V
DD
/2 – 0.3
V
V
LIT+
V
LREF
= 0.42
×
V
DD
—
—
V
LREF
+1
V
V
LIT–
V
LREF
= 0.42
×
V
DD
V
LREF
+0.2
—
—
V
V
O
NOTES:
1. Transmit Max Packet (1 port transmitting max size isochronous packet (4096 bytes), sent on every isochronous interval, S400, data value of
0xCCCCCCCCh), V
DD
= 3.3 V, T
= 25
°
C
2. Receive typical packet (1 port receiving DV packets on every isochronous interval, S100), V
DD
= 3.3 V, T
amb
= 25
°
C
3. Idle (1 Port transmitting cycle starts) V
DD
= 3.3 V, T
amb
= 25
°
C
4. The C/LKON pin is able to drive an isolation circuit according to Figure 5A-20 of the IEEE-1394a-2000 standard.
At rated I
O
current
1.665
—
2.015
V
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