參數(shù)資料
型號： PCD6003
廠商： NXP Semiconductors N.V.
英文描述： Digital telephone answering machine chip
中文描述： 數(shù)字電話應答機芯片
文件頁數(shù)： 74/96頁
文件大?。?/td> 385K
代理商： PCD6003
2001 Apr 17
74
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
16.2.1
P
ORT
1 R
EGISTER
(P1)
The alternative outputs (SDA and SCL) are connected with the general purpose outputs via an AND logic gate. Therefore
when using the alternative functions the corresponding port bits have to be set to a logic 1.
For control of I
2
C-bus peripherals like for instance EEPROMs and LCD displays, P1.6 and P1.7 can also be used as SDA
and SCL to support I
2
C-bus. See Section 10.11 on how to activate this alternative function of P1.6 and P1.7. The rest of
Port 1 is defined as general purpose I/O pins as for the standard 80C51 microcontroller.
Table 68
Port 1 Register (SFR address 90H); bit addressable; reset state FFH
Table 69
P1 pin configuration
16.2.2
P
ORT
3 R
EGISTER
(P3)
Port 3 is defined as a set of 8 general purpose I/O pins similar to the standard 80C51 microcontroller except for P3.6 and
P3.7 which do not have the RD and WR functionality (the RD and WR are separate pins). Table 72 gives the different
functions and the corresponding port configurations available on P3.7, P3.6, P3.1 and P3.0. The last column gives the
function and configuration after reset.
Table 70
P3 (B0H) bit assignment; bit addressable; reset state FFH; note 1
Note
1.
The alternative outputs (for MSK, IOM) are connected with the general purpose outputs via an AND logic gate.
Therefore when using the alternative functions the corresponding port bits have to be set to a logic 1.
Table 71
P3 pin configuration
Table 72
Port 3.7, 3.6, 3.1 and 3.0 modes and configuration
7
6
5
4
3
2
1
0
P1.7/SDA
P1.6/SCL
P1.5
P1.4/EX6
P1.3/EX5
P1.2/EX4
P1.1/EX3
P1.0/EX2
PORT PINS
CONFIGURATION
P1.7 and P1.6
P1.5 to P1.0
open-drain
quasi-bidirectional
7
6
5
4
3
2
1
0
P3.7/MIN/DI
P3.6/MOUT
2/FSC
P3.5/T1
P3.4/T0
P3.3/EX1N
P3.2/EX0N
P3.1/MOUT
1/DCK
P3.0/MOUT
0/DO
PORT PINS
CONFIGURATION
P3.7, P3.6, P3.1 and P3.0
P3.5 to P3.2
see Table 72
quasi-bidirectional
MSK
IOM
GENERAL PURPOSE I/O PORT
(RESET STATE)
SIGNAL
MASTER
SLAVE
MOUT0
MOUT1
MOUT2
MIN
push-pull
push-pull
push-pull
input
DO
DCK
FSC
DI
open-drain 4 mA
push-pull
push-pull
input
open-drain 4 mA
input
input
input
P3.0
P3.1
P3.6
P3.7
quasi-bidirectional
weak pull-up
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