參數(shù)資料
型號(hào)： PCD6003
廠商： NXP Semiconductors N.V.
英文描述： Digital telephone answering machine chip
中文描述： 數(shù)字電話應(yīng)答機(jī)芯片
文件頁(yè)數(shù)： 54/96頁(yè)
文件大小： 385K
代理商： PCD6003
2001 Apr 17
54
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
The internal ROM fetching will be activated by making EA
a logic 1. If EA is logic 0 external program memory can be
connected and the internal ROM will be disabled. The
external memory interface block contains the MA and P2
generation logic and registers.
The P2 and MA latches have special enable signals.
Appropriate bits (MAGP and P2GP) in the control register
make P2 and MA available as general purpose output
ports or as the 80C51 address bus. The last option is
necessary for target debugging (EA = 0), external ROM
(EA = 0) or parallel flash memory (MAGP = 1 and
P2GP = 1). In these cases external latches must be
provided if the application needs the P2/MA as general
purpose output ports as well.
The MAGP and P2GP signals are bit 3 and 4 of the
configuration register latch. MA will be a general purpose
output port when MAGP is set to logic 0 by software
(default after reset). If MAGP is set to logic 1 the MA port
operates as the lower 8 bits of the program/data address
bus. P2 will be a general purpose output port when P2GP
is set to logic 0 by software (default after reset). If P2GP is
set to logic 1 the P2 port operates as the higher 8 bits of
the program/data address bus. The accessability of the
P2GP and MAGP bits of the ConfReg register in the
external interface block depends on the value of the EAM
(P4CFG.5) SFR bit: when EAM is logic 0 (default after
reset), the XRAM-mapped control registers can only be
accessed if P4.3 is logic 1 (compatible mode to PCD6002
DTAM device). Otherwise (i.e. when EAM is logic 0),
XRAM addressing is independent of the value of the P4.3
SFR bit, but needs ARD to be logic 0 (only available when
fetching from internal memory, i.e. EA is logic 1).
The latches are used for the configuration, MA and
P2 registers and they are mapped at addresses
200H to 202H of the external data memory map. Refer to
Table 48.
Register ConfReg (2-bit): this is the Configuration
Register. In this register single bits are set to control the
functionality of the external outputs. The content of this
register is given in Table 49. With the bits P2GP
(P2 General Purpose) and MAGP (MA General
Purpose) the output function of MA and P2 is
determined.
With bit P2GP = 0 (reset value) the output P2 is latched
and can be used as a general purpose output for
example to drive LEDs. Data can be written to the
register P2 with a MOVX command. With P2GP = 1 the
internal bus P2_int[7:0] is directly transferred to the
output P2[7:0]. This mode is for example applied when
using parallel flash. Output P2[7:0] delivers then the
high address byte for the parallel flash.
With MAGP = 0 (reset value MAGP = 0) the output
MA[7:0] can be used as a general purpose output.
Otherwise, output MA[7:0] serves as latch (with ALE as
enable signal) for the low address byte provided by a
internal bus.
Register MA (8-bit): If EA = 1 (internal ROM used) and
MAGP = 0 (default after reset) the MA pins will output
the contents of the MA register (0201H) which contains
00H after reset. The state of the MA pins can be
changed by writing a new value to the MA register. This
must be done with a MOVX instruction while the P4.3 bit
or the EAM bit is logic 1.
Register P2 (8-bit): If EA = 1 (internal ROM used) and
P2GP = 0 (default after reset) the P2 pins will output the
contents of the P2 register (0202H) which contains 00H
after reset. The state of the P2 pins can be changed by
writing a new value to the P2 register.This must be done
with a MOVX instruction while the P4.3 bit or the EAM
bit is logic 1.
Table 47
Overview of P0/MA/P2 settings; notes 1, 2, 3, 4 and 5
Notes
1.
XA/XD: address and data during a MOVX instruction; PA/PD: address and data during a code fetch; GP: general
purpose port; low: low address byte; high: high address byte.
EA
MAGP
P2GP
FUNCTION P0/MA/P2
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
P0 = XA_low/XD/PA_low/PD, MA = XA/PA_low and P2 = XA/PA_high
P0 =XD, MA =GP and P2 = GP
P0 = XD, MA = XA_low and P2 = GP
P0 = XD, MA = GP and P2 = XA_high
P0 = XD, MA = XA_low and P2 = XA_high
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