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參數(shù)資料
| 型號： | PCD6003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | 數(shù)字電話應答機芯片 |
| 文件頁數(shù)： | 32/96頁 |
| 文件大?。?/td> | 385K |
| 代理商： | PCD6003 |
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2001 Apr 17
32
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
10.7
Interface to the Memory Control Block (MCB)
The MCB is a 3-wire serial interface designed to interface
with a versatile range of serial flash memories (both
Microwire and SPI mode 0/3 compatible slave devices) in
parallel with program OTP/external ROM and even
external data SRAM.
The 3-wire serial interface consists of a serial data output
(FSO) serial data input (FSI) and a serial clock signal
(FSK). FSK, FSO and FSI are alternative functions of the
general purpose I/O pins P4.1, P4.2 and P4.4. The serial
interfaceiscontrolledviatheMCSCandMCSDSFRs.The
FSK and FSO outputs are both open-drain and must be
pulled to 3 V with external resistors R
FSK
and R
FSO
. The
recommended value for both resistors at high FSK speeds
(>1 MHz) is 1 k
. The MCSC SFR is defined in
Section 10.7.1.
Turning the MCB on by setting bit MCSC.3, will switch the
FSK and FSO pins to logic 0. A write to MCSD will
generate the appropriate FSK/FSO signal. A read from
MCSD will only generate 8 FSK pulses and will shift-in the
next byte. The shifting and the FSK/FSO signal can be
suppressed by setting bit 2 of MCSC. This can be used for
reading the last byte out of the serial flash memory during
a read sequence. The FSK shift off operation however is
not necessary if the MCB is already turned off when
reading the MCSD SFR for the last time.
If a serial flash memory is chosen the FSK master clock
rate can be selected with bits 0 and 1, as shown in
Table 24. The MCB is always master, which means that
the FSK clock is always generated by the PCD6003.
DependingontheFSKclock rate,the shiftingcancontinue
for8
×
32microcontroller_CLKperiods.Duringthisperiod,
the microcontroller should not be put in a power saving
mode (Idle, Power-down and System-off), otherwise the
shifting will stop.
Data coming from or going to the serial flash memory can
be accessed by means of the MCSD SFR. This is simply
an 8-bit serial shift register. The first FSO and FSI bits are
always the most significant bits of MCSD. The first read of
the MCSD SFR will only serially load the MCSD SFR with
valid data. Therefore, the first read operation must always
be followed with another read operation which reads the
actual received data out of the MCSD SFR.
The serial shifting of bits into and out of MCSD is done at
the same moment: 1 microcontroller clock before the
falling edge of FSK (t
SF
). When the FSK speed is
programmedatthehighestspeed(microcontroller_CLK/4)
this shifting will be done in the middle of the FSK HIGH
level time. The most time-critical situation is when FSK is
only 2 clocks wide and has a frequency of 3.5 MHz
(14 MHz/4). In this case make sure that t
r(FSK)
, which can
be controlled by the value of R
FSK
, is greater than the hold
time requirement of the slave device.
Figure 12 shows how a Microwire compatible device can
beaccessed with an FSK speed of microcontroller_CLK/4.
A SPI mode 0/3 device requires an additional FSK clock
falling edge to trigger the slave device to generate valid
data on the FSI line. The SPI mode 3 can be achieved by
starting with FSK high when the device is turned on (turn
MCBonafterassertingthechipenableoftheslavedevice)
and by ending with FSK. The SPI mode 0 can be achieved
bygeneratinganadditionalFSKpulse(byturningtheMCB
off and on again, see Fig.12) between the last write to
MCSD and the first read of MCSD.
A variety of serial flash memory driver software packages
is included in the API software for the microcontroller that
is provided with the chip.
An application note is available to help implementation of
the software for the SPI.
10.7.1
M
EMORY
C
ONTROL
S
ERIAL
C
OMMAND
R
EGISTER
(MCSC)
Table 23
Memory Control Serial Command Register (SFR address A9H)
Table 24
Selection of FSK clock rate
7
6
5
4
3
2
1
0
spare
spare
spare
spare
MCB on
shift off
FSK rate 1
FSK rate 0
MCSC.1
MCSC.0
FSK CLOCK RATE
0
0
1
1
0
1
0
1
microcontroller_CLK/4
microcontroller_CLK/8
microcontroller_CLK/16
microcontroller_CLK/32
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