參數(shù)資料
型號(hào)： PCD6003
廠(chǎng)商： NXP Semiconductors N.V.
英文描述： Digital telephone answering machine chip
中文描述： 數(shù)字電話(huà)應(yīng)答機(jī)芯片
文件頁(yè)數(shù)： 73/96頁(yè)
文件大?。?/td> 385K
代理商： PCD6003
2001 Apr 17
73
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
16.2
External digital Interfaces
For control of peripherals like a display, ringer, key pad
and line interface a large number of general purpose
digital I/O pins are available in addition to the flash
memory, LCD control pins and MSK or IOM modem pins.
The exact number of free I/O pins depends on the choice
of peripherals that make up the system configuration.
In case all alternative port functions of P1 and P3 are
used, 10 input lines remain available on P1 and P3 of
which 7 are programmable for interrupts.
I/O ports P1 and P3 are ‘weak pull-up’ types which can
therefore be used either as inputs or outputs. The reset
value of P1 and P3 is FFH (input mode). In output mode
for driving with a logic 1 (weak pull-up) the external load of
P1 and P3 should be equivalent to >100 k
, for ‘driving’
with a logic 0 the sink current should not exceed 4 mA.
In addition to P1 and P3 there are 16 output ports
available at P2 and MA. Output Ports P2 and MA are
push-pull ports and their reset value is 00H (output 00H).
The driving level of P2 and MA is 4 mA for either logic 0 or
logic 1. Port P4 provides the flash memory and display
control signals. The P1, P3 and P4 I/O lines are available
as SFR bit-addressable I/O registers in the configuration
shown in Fig.35, while P2 and MA are available as (not bit
addressable) XDATA mapped ports (for exact
configuration and detailed description see Chapter 12).
The MA and P2 ports are described in Chapter 12. The
configuration of Ports P1 and P3 are described in the
Tables 68 to 76.
MGM798
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
0
1
2
3
4
5
6
7
MA
P00
P01
P02
P03
P04
P05
P06
P07
0
1
2
3
4
5
6
7
P0
P1.0/EX2
P1.1/EX3
P1.2/EX4
P1.3/EX5
P1.4/EX6
P1.5
P1.6/SCL
P1.7/SDA
0
1
2
3
4
5
6
7
P1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
0
1
2
3
4
5
6
7
P2
P3.0/MOUT0/DO
P3.1/MOUT1/DCK
P3.2/EX0N
P3.3/EX1N
P3.4/T0
P3.5/T1
P3.6/MOUT2/FSC
P3.7/MIN/DI
0
1
2
3
4
5
6
7
P3
P4.0/LE
P4.1/FSK
P4.2/FSO
P4.3
P4.4/FSI
P4.5/GPC
0
1
2
3
4
5
P4
Fig.35 DTAM general purpose digital I/O
configuration.
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