參數(shù)資料
型號(hào)： PCD6003
廠商： NXP Semiconductors N.V.
英文描述： Digital telephone answering machine chip
中文描述： 數(shù)字電話應(yīng)答機(jī)芯片
文件頁(yè)數(shù)： 62/96頁(yè)
文件大?。?/td> 385K
代理商： PCD6003
2001 Apr 17
62
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
13.2.1
V
OLUME
C
ONTROL
R
EGISTERS
(CDVC1
AND
CDVC2)
The Volume Control Registers are identical and both are reset to 00H. Table 54 is relevant to both registers.
Table 53
Volume Control Register 1 (SFR address BBH); Volume Control Register 2 (SFR address BCH)
Table 54
Digital-to-analog gain values
Note
1.
In these gain values the
4 dB digital gain (software DSP output port gain of
2 dB and DNS path gain of
2 dB) is
not included as in previous PCD600x data sheets.
13.2.2
D
ATA
C
ONTROL
R
EGISTER
(DTCON)
Table 55
Data Control Register (SFR address C7H), reset state 00H
Table 56
Analog-to-digital gain values
Notes
1.
The 3.14 dB digital gain of DDF hardware block is not included here. The nominal values given in this table are
rounded for naming convention. See Section 17.5 for exact typical/maximum gain specifications.
System application should be such that the maximum line input signal level does not exceed the specified value to
avoid distortion (see Section 17.5 for maximum input level specifications). At a maximum line input level of
37 dBm
full-scale control the internal ADC can still be achieved by a maximum gain setting of 35 dB.
System application should be such that the maximum differential microphone input signal level does not exceed the
specified value to avoid distortion (see Section 17.5 for maximum input level specifications). At a maximum
microphone input level of
52 dBmfull-scale control the internal ADCcan still beachieved bya maximum gain setting
of 50 dB. The high dynamic range of the ADC allows for additional digital gain up to 30 dB by the DSP.
If the HI_GAIN1/LO_GAIN2 bit is set to logic 1, the value of bit 3 of CDVC1/2 and AMP_EN is overruled and the gain
will be +35 dB for CODEC1 and +7 dB for CODEC2.
2.
3.
4.
7
6
5
4
3
2
1
0
D/A.1
D/A.0
spare
spare
A/D
spare
spare
spare
CDVC1[7:4]/CDVC2[7:4]
DIGITAL-TO-ANALOG GAIN FOR CODEC1 AND CODEC2
(1)
12 dB
6 dB
0 dB
+6 dB
00XX
01XX
10XX
11XX
7
6
5
4
3
2
1
0
spare
CODEC1 analog-to-digital gain and channel selection
spare
HI_GAIN1
LINESEL
spare
AMP_ENA
CODEC2 analog-to-digital gain
LO_GAIN2
spare
CDVC1[3:0]/CDVC2
[3:0]
ANALOG-TO-DIGITAL GAIN
(1)
CODEC1 (LINE)
(2)
CODEC2 (MIC)
(3)
HI_GAIN1 (LINE)/LO_GAIN2 (MIC)
AMP_ENA = 0 AMP_ENA = 1
0XXX
1XXX
XXXX
7 dB
23 dB
35 dB
23 dB
35 dB
38 dB
50 dB
HI_GAIN1/LO_GAIN2 = 0
(4)
7 dB
HI_GAIN1/LO_GAIN2 = 1
(4)
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