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| 型號： | PCD6003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | 數(shù)字電話應(yīng)答機芯片 |
| 文件頁數(shù)： | 35/96頁 |
| 文件大?。?/td> | 385K |
| 代理商： | PCD6003 |
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2001 Apr 17
35
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
10.8
The test registers CDTRx, PMTRx and TCTRL
The special function registers CDTR1, CDTR2, PMTR1, PMTR2 and TCTRL can put the DSP or CODECs into various
test modes. In these test modes normal operation is not guaranteed. The output behaviour of P3 can be changed and
the DSP test modes can lead to a higher current consumption and to malfunction of the DSP. Three bits however are
accessible by the user: CDTR2.0, PMTR2.0 and PMTR2.2. See Tables 29 and 30 for detailed description.
Table 29
CDTR2 (98H) bit assignment; reset state 00H
Table 30
PMTR2 (98H) bit assignment; reset state 00H
Notes
1.
For minimum current consumption in POTS mode (telephone line supplied operation), two bits of these registers
have to be set (PMTR2.0 = 1, CDTR2.0 = 1).
For best noise performance of the Sigma Delta AD, chopping has to be enabled (PMTR2.2 = 1).
2.
10.9
Interface to Timing and Control Block (TICB)
The interface to the TICB consists of the special function registers SPCON, CKCON and RTCON and the signals
microcontroller_CLK_EN, microcontroller_CLK, FS_event, Time_event and RTC_event. The signals are described in
Section 10.1.
10.10 Power and Interrupt Control Register (PCON)
Table 31
Power and Interrupt Control Register (SFR address 87H); reset state 00H
Table 32
Description of PCON bits
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
reserved
reserved
reserved
avo_off
(1)
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
reserved
atc_chop_en
(2)
reserved
avb_off
(1)
7
6
5
4
3
2
1
0
spare
ARD
spare
WLE/EW
GF1
GF0
PD
IDL
BIT
SYMBOL
ARD
DESCRIPTION
7
6
Spare, may be used as general purpose bit.
AUX-RAM Disable.
If ARD = 1, then the access of a MOVX instruction to the 512 bytes
of the AUX-RAM is disabled. If ARD = 1, then a MOVX operation can access the lower
512 bytes of the external memory. The upper part of the external memory can always
be accessed independently of the setting of the ARD bit.
Spare, may be used as general purpose bit.
Watchdog Load Enable.
This flag must be set by software prior to loading the
Watchdog Timer. The flag is reset when the timer is loaded. See Section 10.10.3
General Purpose Flag 1.
General Purpose Flag 0.
Power-down mode select.
Setting this bit activates the Power-down mode; see
Section 10.10.2.
Idle mode select.
Setting this bit activates the Idle mode; see Section 10.10.2.
5
4
WLE/EW
3
2
1
GF1
GF0
PD
0
IDL
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