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參數(shù)資料
| 型號： | PCD6003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | 數(shù)字電話應(yīng)答機(jī)芯片 |
| 文件頁數(shù)： | 14/96頁 |
| 文件大?。?/td> | 385K |
| 代理商： | PCD6003 |
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2001 Apr 17
14
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
Table 2
Descriptions and frequency values for signals shown in Fig.4
Notes
1.
These values are only valid if the RTC mode bit CKCON.6 has been set according to the PLL_IN frequency used
(see also Table 6).
If the IOM Slave mode is activated, these clock signals are synchronized to the externally applied FSC.
Proper IOM functionality is only guaranteed at DSP clock frequencies of 28 and 42 MHz. If the IOM Slave mode is
activated, the externally applied DCK and FSC signals are used.
These master frequencies do not comply to IOM specification. For 3.58 MHz crystal operation, proper IOM
functionality is therefore only guaranteed in Master mode.
2.
3.
4.
SIGNAL
FUNCTION
VALUE (MHz)
PLL_IN 3.456
PLL_IN 3.580
Microprocessor and DSP clock signals
EMG_CLK
CLK_42
CLK_28
CLK_21
CLK_14
CLK_7
CLK_1
emergency clock
DSP selectable clock frequency
DSP selectable clock frequency
microcontroller selectable clock frequency
microcontroller selectable clock frequency
DSP and microcontroller selectable clock frequency
DSP and microcontroller selectable clock frequency
3.456
41.472
27.648
20.736
13.824
6.912
1.152
3.580
42.960
28.640
21.480
14.320
7.160
1.193
CODEC clock signals
CLK_21
CLK3_EMG
CLK3_CORR
CLK3_OUT
CLK14_CODEC
input clock for phase corrected CLK3_OUT
EMG_CLK input to CLK_3 multiplexer
frequency corrected CODEC clock (24/25
×
3.58 MHz)
phase corrected 3.456 MHz CODEC clock
input clock for CODECs
20.736
3.456
3.456
(1)(2)
13.824
21.480
3.580
3.437
(1)(2)
14.320
IOM clock/timing signals
DCKmaster
FSCmaster
the IOM master clock signal DCK generated by the TICB
the IOM master frame sync FSC generated by the TICB
1.536
(1)(3)
8 kHz
(1)(3)
1.527
(1)(3)(4)
7.955 kHz
(1)(3)(4)
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