參數(shù)資料
型號(hào)： PCD6003
廠商： NXP Semiconductors N.V.
英文描述： Digital telephone answering machine chip
中文描述： 數(shù)字電話應(yīng)答機(jī)芯片
文件頁(yè)數(shù)： 39/96頁(yè)
文件大小： 385K
代理商： PCD6003
2001 Apr 17
39
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
Table 35
I
2
C-bus bit frequencies in Master mode
Note that any I
2
C-bus device tolerates a maximum and sometimes a minimum SCL frequency. The correct setting of bits
CR2, CR1 and CR0 using a specific microcontroller clock frequency is therefore important.
10.11.2 S
TATUS
R
EGISTER
(S1STA)
S1STA is an 8-bit read-only register. Its contents may be used as a vector to a service routine. This optimizes the
response time of the software and consequently the I
2
C-bus.
Table 36
Status Register (SFR address D9H); reset state F8H
10.11.3 D
ATA
S
HIFT
R
EGISTER
(S1DAT)
S1DAT contains the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first.
Table 37
Data Shift Register (SFR address DAH); reset state 00H
10.11.4 A
DDRESS
R
EGISTER
(S1ADR)
This 8-bit ‘own address register’ may be loaded with the 7-bit address to which the controller will respond when
programmed as a slave receiver/transmitter. The LSB bit GC is used to determine whether the general CALL address is
recognized.
Table 38
Address Register (SFR address DBH); reset state 00H
CR2
CR1
CR0
f
microcontroller_clk
DIVIDED BY
I
2
C-BUS BIT FREQUENCY (kHz) at f
microcontroller_clk
0.9 MHz
3.58 MHz
7.16 MHz
358
239
179
89.5
59.7
44.8
14.32 MHz
358
179
119
89.5
21 MHz
269
179
134
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
20
30
40
80
120
160
90
45
30
22
11
7.5
5.6
358
179
119
90
45
30
22
BIT
SYMBOL
DESCRIPTION
7 to 3
2 to 0
SC[4:0]
contains the status code defined by the I
2
C protocol
not used, all bits are 0
BIT
SYMBOL
DESCRIPTION
7 to 0
S1DAT[7:0]
I
2
C-bus serial data
BIT
SYMBOL
DESCRIPTION
7 to 1
0
SLA[6:0]
GC
own I
2
C-bus address
0: general CALL address is not recognized
1: general CALL address is recognized
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