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參數(shù)資料
| 型號： | PCD6003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital telephone answering machine chip |
| 中文描述： | 數(shù)字電話應(yīng)答機芯片 |
| 文件頁數(shù)： | 55/96頁 |
| 文件大小： | 385K |
| 代理商： | PCD6003 |
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2001 Apr 17
55
Philips Semiconductors
Product specification
Digital telephone answering machine chip
PCD6003
2.
Writing MAGP/P2GP is independent of the setting of the P4.3 SFR bit if P4CFG.5 (EAM) is set to logic 1, otherwise
(EAM logic 0) P4.3 must be logic 1.
The WR/RD pins are always active when doing a MOVX. They can be turned inactive for MOVX below 200H by
setting the ARD bit in PCON in case the EAM Bit is set to logic 1.
P0/P2 are standard 80C51 ports. An external latch is not needed since the demultiplexing of P0 is taken over by the
MA port.
The MA/P2/ConfReg registers are part of the auxiliary RAM address space and can be disabled by setting the ARD
bit in PCON in case the EAM Bit is set to logic 1.
3.
4.
5.
Table 48
External memory control registers
Table 49
Configuration Register (ConfReg); reset state 00H
12.1
Supported flash memories
Table 50 shows the ports that are available in an application using various flash memories.
For all types of flash memory shown in Table 50 (except for the parallel flash memory) at least 34 general purpose
I/O pins can be used for the application (display, line interface, keypad and LEDs; for example). P0 can also be used for
the application to connect memory mapped peripherals such as an LCD controller or keypad. P0 pins have no output
latch, so data written to this port will not remain here.
There are many different types of flash memories manufactured, and the PCD6003 will work with many of them. Table 51
explains the most important characteristics of a few of the commercially available flash memories which can be
connected to the PCD6003 directly.
Table 50
Ports available for the application
Note
1.
P0 can be used as a data bus for other peripherals if not conflicting with the flash memory.
EXTERNAL MEMORY CONTROL
REGISTERS
ADDRESS P2/P0
(P4.3 = 1, EAM = 0
or ARD = 0, EAM = 1, EA = 1)
RESET VALUE
ACCESS
ConfReg
MA
P2
0200H
0201H
0202H
00H
00H
00H
R and W
R and W
R and W
7
6
5
4
3
2
1
0
P2GP
MAGP
FLASH
MEMORY
PORTS USED BY FLASH
PORTS AVAILABLE FOR APPLICATION
I/O
I
O
I/O
I/O
P0
(1)
O
CAD
P0
P4.1, P4.2 and P4.3
P1, P3, P4.0,
P4.4 and P4.5
P1, P3,
P4.0 and P4.5
P1, P3 and P4
(except P4.3)
P1, P3,
P4.4 and P4.5
MA and P2
SPI/Microwire
P4.4
P4.1, P4.2 and P4.3
P0
MA and P2
I
2
C-bus
P1.6 and P1.7
P0
(1)
MA, P2 and P4.3
Parallel
P0
MA, P2, P4.0, P4.1,
P4.2 and P4.3
P0
(1)
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