參數(shù)資料
型號(hào)： PC8245MTPU300D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Integrated Processor Family
中文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 51/61頁(yè)
文件大?。?/td> 429K
代理商： PC8245MTPU300D
51
PC8245
2171D–HIREL–06/04
The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE,
AS, MCP, QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and
PLL_CFG[0:4]/DA[10:15]. These pins are sampled during reset to configure the device.
The PLL_CFG[0:4] signals are sampled a few clocks after the negation of HRST_CPU
and HRST_CTRL.
Reset configuration pins should be tied to GND via 1 k
pull-down resistors to ensure a
logic zero level is read into the configuration bits during reset if the default logic-one
level is not desired.
Any other unused active low input pins should be tied to a logic-one level via weak pull-
up resistors (2 k
– 10 k
) to the appropriate power supply listed in Table 1 on page 6.
Unused active high input pins should be tied to GND via weak pull-down resistors (2 k
– 10 k
).
PCI Reference Voltage – LV
DD
The PC8245 PCI reference voltage (L
V
DD
) pins should be connected to 3.3 ± 0.3V power
supply if interfacing the PC8245 into a 3.3V PCI bus system. Similarly, the L
V
DD
pins
should be connected to 5.0V ± 5% power supply if interfacing the PC8245 into a 5V PCI
bus system. For either reference voltage, the PC8245 always performs 3.3V signaling
as described in the PCI Local Bus Specification (Rev. 2.2). The PC8245 tolerates 5V
signals when interfaced into a 5V PCI bus system.
PC8245 Compatibility with
PC8240
The PC8245 AC timing specifications are backwards-compatible with those of
the PC8240, except for the requirements of item 11
in Table 9 on page 31. Timing
adjustments are needed as specified for T
OS
(SDRAM_SYNC_IN to
sys_logic_clk
offset) time requirements.
The PC8245 does not support the SDRAM flow-through memory interface.
The nominal core
V
DD
power supply changes from 2.5V on the PC8240 to 1.8/2.0V on
the PC8245. See Table “Recommended Operating Conditions” on page 12 for details.
The PC8245 PLL_CFG[0:4] setting 0x02 (0b00010) has a different ‘PCI to Mem’ and
‘Mem to CPU’ multiplier ratio than the same setting on the PC8240, and thus, is not
backwards-compatible. See Table 16 on page 45 for details.
The PC8245 PLL_CFG[0:4] settings 0x08 (0b01000), 0x0C (0b01100), 0x12 (0b10010),
0x18 (0b11000), 0x1C (0b11100), and 0x1D (0b11101) are capable of accepting a sub-
set of the PCI_SYNC_IN input frequency range of that of the PC8240, and thus, may not
be fully backwards-compatible. See Table 16 on page 45 for details.
There are two additional reset configuration signals on the PC8245 which are not used
as reset configuration signals on the PC8240: SDMA0 and SDMA1.
The SDMA0 reset configuration pin selects between the PC8245 DUART or the PC8240
backwards compatible mode PCI_CLK[0:4] functionality on these multiplexed signals.
The default state (logic 1) of SDMA0 selects the PC8240 backwards compatible mode
of PCI_CLK[0:4] functionality while a logic 0 state on the SDMA0 signal selects DUART
functionality. Note if using the DUART mode, four of the five PCI clocks, PCI_CLK[0:3],
are not available.
The SDMA1 reset configuration pin selects between PC8245 extended ROM functional-
ity or PC8240 backwards-compatible functionality on the multiplexed signals: TBEN,
CHKSTOP_IN, SRESET, TRIG_IN, and TRIG_OUT. The default state (logic 1) of
SDMA1 selects the PC8240 backwards compatible mode functionality, while a logic 0
state on the SDMA1 signal selects extended ROM functionality. Note if using the
extended ROM mode, TBEN, CHKSTOP_IN, SRESET, TRIG_IN, and TRIG_OUT func-
tionality are not available.
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