參數資料
型號: PC8245MTPU300D
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Integrated Processor Family
中文描述: 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.27 MM PITCH, TBGA-352
文件頁數: 3/61頁
文件大小: 429K
代理商: PC8245MTPU300D
3
PC8245
2171D–HIREL–06/04
The peripheral logic integrates a PCI bridge, dual universal asynchronous
receiver/transmitter (DUART), memory controller, DMA controller, EPIC interrupt con-
troller, a message unit (and I
2
O interface), and a I
2
C inteface controller. The processor
core is a full-featured, high-performance processor with floating-point support, memory
management, 16-Kbyte instruction cache, 16-Kbyte data cache, and power manage-
ment features. The integration reduces the overall packaging requirements and the
number of discrete devices required for an embedded system.
The PC8245 contains an internal peripheral logic bus that interfaces the processor core
to the peripheral logic. The core can operate at a variety of frequencies, allowing the
designer to trade-off performance for power consumption. The processor core is
clocked from a separate PLL, which is referenced to the peripheral logic PLL. This
allows the microprocessor and the peripheral logic block to operate at different frequen-
cies, while maintaining a synchronous bus interface. The interface uses a 64- or 32-bit
data bus (depending on memory data bus width) and a 32-bit address bus along with
control signals that enable the interface between the processor and peripheral logic to
be optimized for performance. PCI accesses to the PC8245 memory space are passed
to the processor bus for snooping when snoop mode is enabled.
The processor core and peripheral logic are general-purpose in order to serve a variety
of embedded applications. The PC8245 can be used as either a PCI host or PCI agent
controller.
General Parameters
The following list provides a summary of the general parameters of the PC8245:
Technology0.25 μm CMOS, five-layer metal
Die size
49.2 mm
2
Transistor count4.5 million
Logic designFully static
PackagesSurface-mount 352 tape ball grid array (TBGA)
Core power supply:2.0V ± 100 mV DC
(nominal; see Table “Recommended Operating Conditions” on page 12
for details
I/O power supply3.0 to 3.6V DC
Features
Major features of the PC8245 are as follows:
Processor core
High-performance, superscalar processor core
Integer unit (IU), floating-point unit (FPU) (software enabled or disabled),
load/store unit (LSU), system register unit (SRU), and a branch processing
unit (BPU)
16-Kbyte instruction cache
16-Kbyte data cache
Lockable L1 caches
entire cache or on a per-way basis up to three of four
ways
Dynamic power management
supports 60x nap, doze, and sleep modes
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