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參數(shù)資料
| 型號： | PC8245MTPU300D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, TBGA-352 |
| 文件頁數(shù)： | 31/61頁 |
| 文件大小： | 429K |
| 代理商： | PC8245MTPU300D |
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31
PC8245
2171D–HIREL–06/04
Input AC Timing
Specifications
Table 9 provides the input AC timing specifications at recommended operating condi-
tions (see Table “Recommended Operating Conditions” on page 12) with L
V
DD
= 3.3V ±
0.3V. See Figure 13 and Figure 14.
Notes:
1. All PCI signals are measured from OV
DD
/2 of the rising edge of PCI_SYNC_IN to 0.4 x OV
DD
of the signal in question for
3.3V PCI signaling levels. See Figure 14.
2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in
question to the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same
as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on
every rising and falling edge of PCI_SYNC_IN). See Figure 13.
3. Input timings are measured at the pin.
4. T
CLK
is the time of one SDRAM_SYNC_IN clock cycle.
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM
= 1.4V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 15.
6. The memory interface input setup and hold times are programmable to four possible combinations by programming bits 5:4
of register offset <0x77> to select the desired input setup and hold times.
7. Tos represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present
on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM clocks become
offset by the delay amount. The feedback trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened by
this amount relative to the SDRAM clock output trace lengths to maintain phase-alignment of the memory clocks with
respect to sys_logic_clk.
Note that the DLL locking range graphs of Figure 9 through Figure 12 compensate for
Tos and there is no additional requirement to shorten Tloop by the duration of Tos. Refer to Motorola Applica-
tion Note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for more details on accommodating
for the problem of Tos and trace measurements in general.
Table 9.
Input AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
10a
PCI Input Signals Valid to PCI_SYNC_IN (Input Setup)
3.0
–
ns
(1)(3)
10b
Memory Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
10b0
Tap 0, Register Offset <0x77>, Bits 5:4 = 0b10
2.6
–
ns
(2)(3)(6)
10b1
Tap 1, Register Offset <0x77>, Bits 5:4 = 0b11
1.9
–
10b2
Tap 2, Register Offset <0x77>, Bits 5:4 = 0b00 (Default)
1.2
–
10b3
Tap 3, Register Offset <0x77>, Bits 5:4 = 0b01
0.5
–
10c
Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
3.0
–
ns
(2)(3)
10d
Two-wire interface
Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
3.0
–
ns
(2)(3)
10e
Mode Select Inputs Valid to HRST_CPU/HRST_CTRL (Input Setup)
9 x T
CLK
–
ns
(2)(3)(4)(5)
11
T
os
– SDRAM_SYNC_IN to sys_logic_clk offset time
0.65
1.0
ns
(7)
11a
SDRAM_SYNC_IN to Memory Signal Inputs Invalid (Input Hold)
11a0
Tap 0, Register Offset <0x77>, Bits 5:4 = 0b10
0
–
ns
(2)(3)(6)
11a1
Tap 1, Register Offset <0x77>, Bits 5:4 = 0b11
0.7
–
11a2
Tap 2, Register Offset <0x77>, Bits 5:4 = 0b00 (Default)
1.4
–
11a3
Tap 3, Register Offset <0x77>, Bits 5:4 = 0b01
2.1
–
11b
HRST_CPU/HRST_CTRL to Mode Select Inputs Invalid (Input Hold)
0
–
ns
(2)(3)(5)
11c
PCI_SYNC_IN to Inputs Invalid (Input Hold)
1.0
–
ns
(1)(2)(3)
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