參數(shù)資料
型號(hào)： PC8245MTPU300D
廠商： ATMEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： Integrated Processor Family
中文描述： 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.27 MM PITCH, TBGA-352
文件頁(yè)數(shù)： 46/61頁(yè)
文件大?。?/td> 429K
代理商： PC8245MTPU300D
46
PC8245
2171D–HIREL–06/04
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Limited by maximum system memory interface operating frequency (100 MHz at 350 MHz CPU).
3. Limited by minimum memory VCO frequency (133 MHz).
4. Limited due to maximum memory VCO frequency (372 MHz).
5. Limited by maximum CPU operating frequency (266 MHz).
6. Limited by minimum CPU VCO frequency (360 MHz).
7. Limited by maximum CPU VCO frequency (800 MHz).
8. In clock off mode, no clocking occurs inside the PC8245 regardless of the PCI_SYNC_IN input.
9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
10. PLL_CFG[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved.
11. Multiplier ratios for this PLL_CFG[0:4] setting are different from the PC8240 and are not backwards-compatible.
12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the PC8240 and may not be fully backwards-compatible.
13. Bits 7
–
4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is dis-
abled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling support.
The AC timing specifications given in this document do not apply in PLL bypass mode.
15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic
PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input sig-
nal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The
PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling
support. The AC timing specifications given in this document do not apply in dual PLL bypass mode.
16. Limited by maximum system memory interface operating frequency (133 MHz at 266 MHz CPU).
17. Limited by minimum CPU operating frequency (100 MHz).
18. Limited by minimum memory bus frequency (50 MHz).
19. PCI_SYNC_IN range for this PLL_CFG[0:4] setting does not exist on the PC8240 and may not be fully backwards-
compatible.
20. No longer supported.
19
11001
(19)
36
(6)
– 53
(5)
72 – 106
180 – 265
36
(6)
– 59
(2)
72 – 118
180 – 295
2
(2)
2.5
(2)
1A
11010
(12)
50
(18)
– 66
(1)
50 – 66
200 – 264
50
(18)
–
66
(1)
50 – 66
200 – 264
1
(4)
4
(2)
1B
11011
(19)
33
(6)
– 44
(5)
66 – 88
198 – 264
33
(6)
– 50
(5)
66 – 100
198 – 300
2
(2)
3
(2)
1C
11100
(12)
44
(6)
– 59
(5)
66 – 88
198 – 264
44
(6)
– 66
(1)
66 – 99
198 – 297
1.5
(2)
3
(2)
1D
11101
(12)
48
(6)
– 66
(1)
72 – 99
198 – 248
48
(6)
– 66
(1)
72 – 99
180 – 248
1.5
(2)
2.5
(2)
1E
11110
(8)
Not Usable
Not Usable
Off
Off
1F
11111
(8)
Not Usable
Not Usable
Off
Off
Table 16.
PLL Configurations (266 and 300 MHz Parts) (Continued)
Ref
PLL_ CFG
[0:4]
(10)(13)
266 MHz Part
(9)
300 MHz Part
(9)
Multipliers
PCI Clock
Input (PCI_
SYNC_IN)
Range
(1)
(MHz)
Periph
Logic/
Mem Bus
Clock
Range
(MHz)
CPU Clock
Range
(MHz)
PCI Clock
Input
(PCI_
SYNC_IN)
Range
(1)
(MHz)
Periph
Logic/Mem
Bus Clock
Range
(MHz)
CPU
Clock
Range
(MHz)
PCI to
Mem
(Mem
VCO)
Mem to
CPU
(CPU
VCO)
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