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| 型號： | PC8245MTPU300D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, TBGA-352 |
| 文件頁數(shù)： | 26/61頁 |
| 文件大小： | 429K |
| 代理商： | PC8245MTPU300D |
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26
PC8245
2171D–HIREL–06/04
2. Specification value at maximum frequency of operation.
3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew
added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance
between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew between
SDRAM_CLKs can be measured, the relationship between the internal sys_logic_clk and the external SDRAM_SYNC_IN
cannot be measured and is guaranteed by design.
4. Relock time is guaranteed by design and characterization. Relock time is not tested.
5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable
V
DD
and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been dis-
abled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted for
a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.
6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (1 or 2). T
CLK
is the period of one
SDRAM_SYNC_OUT clock cycle in ns. T
loop
is the propagation delay of the DLL synchronization feedback loop (PC board
runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) cor-
responds to approximately 1 ns of delay. T
fix0
is a fixed delay inherent in the design when the DLL is at tap point 0 and the
DLL is contributing no delay; T
fix0
equals approximately 3 ns. See Figure 9 through Figure 12 for DLL locking ranges.
7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are
not tested.
Figure 8.
PCI_SYNC-IN Input Clock Timing Diagram
Figure 9 through Figure 12 show the DLL locking range loop delay vs. frequency of operation.These graphs define the
areas of DLL locking for various modes. The grey areas represent where the DLL will lock.
Note also that the DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished by
increasing the time between each of the 128 tap points in the delay line. Although this increased time makes it easier to
guarantee that the reference clock will be within the DLL lock range, it also means there may be slightly more jitter in the
output clock of the DLL, should the phase comparator shift the clock between adjacent tap points.
1
2
3
5a
5b
VM
VM
VM
CVIH
CVIL
VM = Midpoint Voltage (1.4V)
PCI_SYNC_IN
Table 8.
T
dp
(max) and T
dp
(min)
Mode
T
dp
(min)
T
dp
(max)
Unit
Normal tap delay: Bit 2 (DLL_MAX_DELAY) at offset 0 x 76 is cleared
7.58
12.97
ns
Maximum tap delay: Bit 2 (DLL_MAX_DELAY) at offset 0 x 76 is set
8.28
17.57
ns
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