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| 型號： | PC8245MTPU300D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.27 MM PITCH, TBGA-352 |
| 文件頁數(shù)： | 33/61頁 |
| 文件大小： | 429K |
| 代理商： | PC8245MTPU300D |
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33
PC8245
2171D–HIREL–06/04
Figure 15.
Input Timing Diagram for Mode Select Signals
Output AC Timing
Specification
Table 10 provides the processor bus AC timing specifications for the PC8245 at recom-
mended operating conditions (see Table “Recommended Operating Conditions” on
page 12) with L
V
DD
= 3.3V ± 0.3V. See Figure 13 on page 32. All output timings assume
a purely resistive 50
load (see Figure 16 on page 34). Output timings are measured at
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the
system. These specifications are for the default driver strengths indicated in Table 5 on
page 24.
Notes:
1. All PCI signals are measured from GV
DD
_OV
DD
/2 of the rising edge of PCI_SYNC_IN to 0.285
×
OV
DD
or 0.615
×
OV
DD
of
the signal in question for 3.3V PCI signaling levels. See Figure 14 on page 32.
2. All memory and related interface output signal specifications are specified from the VM = 1.4V of the rising edge of the mem-
ory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as
PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on
every rising and falling edge of PCI_SYNC_IN). See Figure 13 on page 32.
VM
VM = Midpoint Voltage (1.4V)
11b
MODE PINS
10e
HRST_CPU/HRST_CTRL
2.0V
0.8V
Table 10.
Output AC Timing Specifications
Num
Characteristics
Min
Max
Unit
Notes
12a
PCI_SYNC_IN to Output Valid, see Figure 17 on page 35
12a0
Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (Default)
–
6.0
ns
(1)(3)
12a1
Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10
–
6.5
12a2
Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI
–
7.0
12a3
Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00
–
7.5
12b
SDRAM_SYNC_IN to Output Valid (Memory Control and Data Signals)
–
4.5
ns
(2)
12c
SDRAM_SYNC_IN to Output Valid (For All Others)
–
7.0
ns
(2)
12d
SDRAM_SYNC_IN to Output Valid (For
Two-wire interface
)
–
5.0
ns
(2)
12e
SDRAM_SYNC_IN to Output Valid (ROM/Flash/PortX)
–
6.0
ns
(2)
13a
Output Hold (PCI), see Figure 17
13a0
Tap 0, PCI_HOLD_DEL = 00, [MCP,CKE] = 11, 66 MHz PCI (Default)
2.0
–
ns
(1)(3)(4)
13a1
Tap 1, PCI_HOLD_DEL = 01, [MCP,CKE] = 10
2.5
–
13a2
Tap 2, PCI_HOLD_DEL = 10, [MCP,CKE] = 01, 33 MHz PCI
3.0
–
13a3
Tap 3, PCI_HOLD_DEL = 11, [MCP,CKE] = 00
3.5
–
13b
Output Hold (All Others)
1.0
–
ns
(2)
14a
PCI_SYNC_IN to Output High Impedance (For PCI)
–
14.0
ns
(1)(3)
14b
SDRAM_SYNC_IN to Output High Impedance (For All Others)
–
4.0
ns
(2)
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