參數(shù)資料
型號： P16F877
廠商： Microchip Technology Inc.
英文描述： DMOS MICROSTEPPING DRVR W/TRANSLATOR
中文描述： 28/40-Pin 8位CMOS閃存微控制器
文件頁數(shù)： 207/218頁
文件大?。?/td> 3824K
代理商： P16F877
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2001 Microchip Technology Inc.
DS30292C-page 205
PIC16F87X
Bus Collision During a Repeated
START Condition (Case 1)
........................92
Bus Collision During a Repeated
START Condition (Case2)
.........................92
Bus Collision During a START
Condition (SCL = 0)
...................................91
Bus Collision During a STOP Condition
.....................93
Bus Collision for Transmit and Acknowledge
.............89
Capture/Compare/PWM
...........................................166
CLKOUT and I/O
......................................................163
I
2
C Bus Data
............................................................171
I
2
C Bus START/STOP bits
......................................170
I
2
C Master Mode First START Bit Timing
..................80
I
2
C Master Mode Reception Timing
...........................85
I
2
C Master Mode Transmission Timing
......................83
Master Mode Transmit Clock Arbitration
....................88
Power-up Timer
.......................................................164
Repeat START Condition
..........................................81
RESET
.....................................................................164
SPI Master Mode
.......................................................70
SPI Slave Mode (CKE = 1)
........................................71
SPI Slave Mode Timing (CKE = 0)
.............................71
Start-up Timer
..........................................................164
STOP Condition Receive or Transmit
........................87
Time-out Sequence on Power-up
.................... 127
,
128
Timer0
......................................................................165
Timer1
......................................................................165
USART Asynchronous Master Transmission
...........100
USART Asynchronous Reception
............................102
USART Synchronous Receive
.................................173
USART Synchronous Reception
..............................108
USART Synchronous Transmission
................ 106
,
173
USART, Asynchronous Reception
...........................104
Wake-up from SLEEP via Interrupt
..........................133
Watchdog Timer
.......................................................164
TMR0
.................................................................................17
TMR0 Register
...................................................................15
TMR1CS bit
........................................................................51
TMR1H
...............................................................................17
TMR1H Register
................................................................15
TMR1L
...............................................................................17
TMR1L Register
.................................................................15
TMR1ON bit
.......................................................................51
TMR2
.................................................................................17
TMR2 Register
...................................................................15
TMR2ON bit
.......................................................................55
TOUTPS0 bit
......................................................................55
TOUTPS1 bit
......................................................................55
TOUTPS2 bit
......................................................................55
TOUTPS3 bit
......................................................................55
TRISA Register
..................................................................16
TRISB Register
..................................................................16
TRISC Register
..................................................................16
TRISD Register
..................................................................16
TRISE Register
.......................................................16
,
36
,
37
IBF Bit
........................................................................37
IBOV Bit
.....................................................................37
OBF Bit
......................................................................37
PSPMODE Bit
...........................................35
,
36
,
37
,
38
TXREG
...............................................................................17
TXSTA Register
................................................................. 95
BRGH Bit
................................................................... 95
CSRC Bit
................................................................... 95
SYNC Bit
................................................................... 95
TRMT Bit
.................................................................... 95
TX9 Bit
....................................................................... 95
TX9D Bit
.................................................................... 95
TXEN Bit
.................................................................... 95
U
UA
...................................................................................... 66
Universal Synchronous Asynchronous Receiver
Transmitter.
See
USART
Update Address, UA
.......................................................... 66
USART
............................................................................... 95
Address Detect Enable (ADDEN Bit)
......................... 96
Asynchronous Mode
.................................................. 99
Asynchronous Receive
............................................ 101
Associated Registers
....................................... 102
Block Diagram
................................................. 101
Asynchronous Receive (9-bit Mode)
........................ 103
Associated Registers
....................................... 104
Block Diagram
................................................. 103
Timing Diagram
............................................... 104
Asynchronous Receive with Address Detect.
See
Asynchronous Receive (9-bit Mode).
Asynchronous Reception
......................................... 102
Asynchronous Transmitter
......................................... 99
Baud Rate Generator (BRG)
..................................... 97
Baud Rate Formula
........................................... 97
Baud Rates, Asynchronous Mode (BRGH=0)
... 98
High Baud Rate Select (BRGH Bit)
................... 95
Sampling
............................................................ 97
Clock Source Select (CSRC Bit)
................................ 95
Continuous Receive Enable (CREN Bit)
.................... 96
Framing Error (FERR Bit)
.......................................... 96
Mode Select (SYNC Bit)
............................................ 95
Overrun Error (OERR Bit)
.......................................... 96
RC6/TX/CK Pin
.........................................................7
,
9
RC7/RX/DT Pin
.........................................................7
,
9
RCSTA Register
........................................................ 96
Receive Data, 9th bit (RX9D Bit)
............................... 96
Receive Enable, 9-bit (RX9 Bit)
................................. 96
Serial Port Enable (SPEN Bit)
..............................95
,
96
Single Receive Enable (SREN Bit)
............................ 96
Synchronous Master Mode
...................................... 105
Synchronous Master Reception
............................... 107
Associated Registers
....................................... 107
Synchronous Master Transmission
......................... 105
Associated Registers
....................................... 106
Synchronous Slave Mode
........................................ 108
Synchronous Slave Reception
................................. 109
Associated Registers
....................................... 109
Synchronous Slave Transmit
................................... 108
Associated Registers
....................................... 108
Transmit Block Diagram
............................................ 99
Transmit Data, 9th Bit (TX9D)
................................... 95
Transmit Enable (TXEN Bit)
...................................... 95
Transmit Enable, Nine-bit (TX9 Bit)
........................... 95
Transmit Shift Register Status (TRMT Bit)
................ 95
TXSTA Register
......................................................... 95
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