
2001 Microchip Technology Inc.
DS30292C-page 17
PIC16F87X
Bank 2
100h
(3)
101h
102h
(3)
103h
(3)
104h
(3)
105h
106h
107h
108h
109h
10Ah
(1,3)
10Bh
(3)
10Ch
10Dh
10Eh
10Fh
Bank 3
180h
(3)
181h
182h
(3)
183h
(3)
184h
(3)
185h
186h
187h
188h
189h
18Ah
(1,3)
18Bh
(3)
18Ch
18Dh
18Eh
18Fh
Legend:
INDF
TMR0
PCL
STATUS
FSR
—
PORTB
—
—
—
PCLATH
INTCON
EEDATA
EEADR
EEDATH
EEADRH
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter
’
s (PC) Least Significant Byte
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
T0IE
INTE
EEPROM Data Register Low Byte
EEPROM Address Register Low Byte
—
—
EEPROM Data Register High Byte
—
—
—
EEPROM Address Register High Byte
0000 0000
27
47
26
18
27
—
31
—
—
—
26
20
41
41
41
41
xxxx xxxx
0000 0000
PD
Z
DC
C
0001 1xxx
xxxx xxxx
—
xxxx xxxx
—
—
—
---0 0000
RBIE
T0IF
INTF
RBIF
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
INDF
OPTION_REG
PCL
STATUS
FSR
—
TRISB
—
—
—
PCLATH
INTCON
EECON1
EECON2
—
—
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as
‘
0
’
.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as
‘
0
’
.
5:
PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
T0IE
INTE
EEPGD
—
—
—
EEPROM Control Register2 (not a physical register)
Reserved maintain clear
Reserved maintain clear
0000 0000
27
19
26
18
27
—
31
—
—
—
26
20
PSA
PS2
PS1
PS0
1111 1111
0000 0000
PD
Z
DC
C
0001 1xxx
xxxx xxxx
—
1111 1111
—
—
—
---0 0000
RBIE
WRERR
T0IF
WREN
INTF
WR
RBIF
RD
0000 000x
x--- x000
41, 42
41
—
—
---- ----
0000 0000
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on
page: