
PIC16F87X
DS30292C-page 16
2001 Microchip Technology Inc.
Bank 1
80h
(3)
81h
82h
(3)
83h
(3)
84h
(3)
85h
86h
87h
88h
(4)
89h
(4)
8Ah
(1,3)
8Bh
(3)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
—
—
SSPCON2
PR2
SSPADD
SSPSTAT
—
—
—
TXSTA
SPBRG
—
—
—
—
ADRESL
ADCON1
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as
‘
0
’
.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Bits PSPIE and PSPIF are reserved on PIC16F873/876 devices; always maintain these bits clear.
3:
These registers can be addressed from any bank.
4:
PORTD, PORTE, TRISD, and TRISE are not physically implemented on PIC16F873/876 devices; read as
‘
0
’
.
5:
PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
—
—
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
IBF
OBF
IBOV
PSPMODE
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
T0IE
INTE
PSPIE
(2)
ADIE
RCIE
TXIE
—
(5)
—
EEIE
—
—
—
—
Unimplemented
Unimplemented
GCEN
ACKSTAT
ACKDT
ACKEN
Timer2 Period Register
Synchronous Serial Port (I
2
C mode) Address Register
SMP
CKE
D/A
P
Unimplemented
Unimplemented
Unimplemented
CSRC
TX9
TXEN
SYNC
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low Byte
ADFM
—
—
—
0000 0000
27
19
26
18
27
29
31
33
35
37
26
20
21
23
25
—
—
68
55
PSA
PS2
PS1
PS0
1111 1111
0000 0000
PD
Z
DC
C
0001 1xxx
xxxx xxxx
--11 1111
1111 1111
1111 1111
1111 1111
—
PORTE Data Direction Bits
0000 -111
---0 0000
RBIE
SSPIE
BCLIE
—
T0IF
CCP1IE
—
—
INTF
TMR2IE
—
POR
RBIF
TMR1IE
CCP2IE
BOR
0000 000x
0000 0000
-r-0 0--0
---- --qq
—
—
RCEN
PEN
RSEN
SEN
0000 0000
1111 1111
0000 0000
73, 74
66
—
—
—
95
97
—
—
—
—
116
112
S
R/W
UA
BF
0000 0000
—
—
—
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
—
—
—
—
xxxx xxxx
PCFG3
PCFG2
PCFG1
PCFG0
0--- 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on
page: