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參數(shù)資料
| 型號(hào)： | OR4E6 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁(yè)數(shù)： | 56/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E6 |
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56
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
FPGA States of Operation
(continued)
The high during configuration (HDC), low during config-
uration (
LDC
), and DONE signals are active outputs in
the FPGA’s initialization and configuration states. HDC,
LDC
, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
If configuration has begun, an assertion of
RESET
or
PRGM
initiates an abort, returning the FPGA to the ini-
tialization state. The
PRGM
and
RESET
pins must be
pulled back high before the FPGA will enter the config-
uration state. During the start-up and operating states,
only the assertion of
PRGM
causes a reconfiguration.
In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after
INIT
goes high.
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
cycles applied to the FPGA. As each configuration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal configuration memory. The configuration load-
ing process is complete when the internal length count
equals the loaded length count in the length count field,
and the required end of configuration frame is written.
During configuration, the PIO and PLC latches/FFs are
held set/reset and the internal BIDI buffers are
3-stated. The combinatorial logic begins to function as
the FPGA is configured. Figure 34 shows the general
waveform of the initialization, configuration, and start-
up states.
Configuration
The ORCA Series FPGA functionality is determined by
the state of internal configuration RAM. This configura-
tion RAM can be loaded in a number of different
modes. In these configuration modes, the FPGA can
act as a master or a slave of other devices in the sys-
tem. The decision as to which configuration mode to
use is a system design issue. Configuration is dis-
cussed in detail, including the configuration data format
and the configuration modes used to load the configu-
ration data in the FPGA, following a description of the
start-up state.
Start-Up
After configuration, the FPGA enters the start-up
phase. This phase is the transition between the config-
uration and operational states and begins when the
number of CCLKs received after
INIT
goes high is equal
to the value of the length count field in the configuration
frame and when the end of configuration frame has
been written. The system design issue in the start-up
phase is to ensure the user I/Os become active without
inadvertently activating devices in the system or caus-
ing bus contention. A second system design concern is
the timing of the release of global set/reset of the PLC
latches/FFs.
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