參數(shù)資料
型號(hào): NANDBAR4N1BZBC5F
廠商: NUMONYX
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA137
封裝: 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-137
文件頁數(shù): 7/52頁
文件大小: 1126K
代理商: NANDBAR4N1BZBC5F
NANDxxxxNx
Description
15/52
Table 3.
Signal names
Signal
Function
Direction
NAND flash memory
I/O0-I/O7
Data input/outputs (x8/x16)
Input/output
I/O8-I/O15
Data inputs/outputs (x16)
Input/output
AL
Address Latch Enable
Input
CL
Command Latch Enable
Input
EF
Chip Enable
Input
R
Read Enable
Input
RB
Ready/Busy (open-drain output)
Output
WF
Write Enable
Input
WP
Write Protect
Input
VDDF
Supply voltage
Power supply
VSSF
Ground
LPSDRAM
A0-Ax
Address inputs - A10 determines the precharge mode
Input
BA0-BA1
Bank Select inputs
Input
DQ0-DQ15
Data inputs/outputs (x16/x32)
Input/output
DQ16-DQ31
Data inputs/outputs (x32)
Input/output
DQS0(1)
1.
Only available with DDR x32.
Data Read/Write Strobe for DQ0-DQ7
Input/output
Data Read/Write Strobe for DQ8-DQ15
Input/output
Data Read/Write Strobe for DQ15-DQ23
Input/output
Data Read/Write Strobe for DQ24-DQ31
Input/output
K
Clock inputs
Input
K (2)
2.
Only available with DDR.
Clock inputs
Input
KE
Clock Enable input
Input
ED
Chip Select inputs
Input
WD
Write Enable input
Input
RAS
Row Address Strobe input
Input
CAS
Column Address Strobe input
Input
DQM0
DQ Mask Enable input controls DQ0-DQ7
Input
DQM1
DQ Mask Enable input controls DQ8-DQ15
Input
DQM2(3)
3.
Only available with SDR/DDR x32.
DQ Mask Enable input controls DQ16-DQ23
Input
DQ Mask Enable input controls DQ24-DQ31
Input
LDQS/UDQS(4)
4.
Only available with DDR x16.
Lower/Upper Data Read/Write Strobe I/O
Input/output
VDDD
Supply voltage
Power supply
VDDQD
Input/output supply voltage
Power supply
VSSQD
Input/output ground
Ground
VSSD
Ground
NC
Not connected internally
DU
Do not use
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