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參數(shù)資料
| 型號： | NANDBAR4N1BZBC5F |
| 廠商： | NUMONYX |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA137 |
| 封裝： | 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-137 |
| 文件頁數(shù)： | 20/52頁 |
| 文件大小： | 1126K |
| 代理商： | NANDBAR4N1BZBC5F |
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Signal descriptions
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When selecting the addresses the LPSDRAM must be enabled, the Row Address Strobe,
RAS, must be Low, VIL, the Column Address Strobe, CAS, and W must be High, VIH.
2.13
LPSDRAM Data inputs/outputs (DQ0-DQ31)
On the LPSDRAM, DQ0-DQ31 output the data stored at the selected address during a read
operation, or are used to input the data during a write operation.
DQ16-DQ31 data inputs/outputs are only available in 32-bit bus width mode.
2.14
LPSDRAM Chip Select (ED)
The Chip Select input ED activates the LPSDRAM state machine, address buffers, and
decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.15
LPSDRAM Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A8-A0 and
BA1-BA0, to select the starting column location prior to a read or write operation.
2.16
LPSDRAM Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A11-A0 and
BA1-BA0 to select the starting address location prior to a read or write operation.
2.17
LPSDRAM Write Enable (WD)
The LPSDRAM Write Enable input, WD, controls writing to the LPSDRAM.
2.18
LPSDRAM Clock Input (K)
The Clock signal, K, is used to clock the read and write cycles on the LPSDRAM. During
normal operation, the Clock Enable pin, KE, is High, VIH. The Clock signal K can be
suspended to switch the device to the self-refresh, power-down or deep power-down mode
by driving KE Low, VIL.
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| NANDBAR4N2AZBA5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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| NANDBBR4E5AP4R5E | 制造商:Micron Technology Inc 功能描述:64MX16/128MX16 MCP PLASTIC PBF VFBGA 1.8V COMBO - Trays |
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