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參數(shù)資料
| 型號： | NANDBAR4N1BZBC5F |
| 廠商： | NUMONYX |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA137 |
| 封裝： | 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-137 |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 1126K |
| 代理商： | NANDBAR4N1BZBC5F |
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Signal descriptions
NANDxxxxNx
2.19
LPSDRAM Clock Input (K)
The Clock signal, K, is only available on the DDR LPSDRAM. It is used in conjunction with
the Clock signal, K.
All LPSDRAM input signals except DQM0/DQM1/DQM2/DQM3, UDQS/LDQS and DQ0-
DQ31 are referred to the cross point of K rising edge and K falling edge.
2.20
LPSDRAM Clock Enable (KE)
The Clock Enable, KE, pin is used by the LPSDRAM to control the synchronizing of the
signals with Clock signal K. If KE is High, VIH, the next Clock rising edge is valid. When KE
is Low, VIL, the signals are no longer clocked and data read and write cycles are extended.
KE is also involved in switching the device to the self-refresh, power-down and deep power-
down modes.
2.21
LPSDRAM lower/upper data input/output mask (DQM0 to
DQM3)
Data Mask Enable inputs, DQM0, DQM1, DQM2, and DQM3 are used to mask the read or
write data. DQM2 and DQM3 are only available in 32-bit bus width mode.
2.22
DQS0 to DQS3 input/outputs
DQS0 to DQS3 can be either input or output signals and act as Write Data Strobe and Read
Data Strobe, respectively. Each DQS signal corresponds to eight DQ pins.
2.23
Lower/Upper Data Read/Write Strobe input/output (LDQS,
UDQS)
LDQS and UDQS can be either input or output signals, and act as Write Data Strobe and
Read Data Strobe respectively. LDQS and UDQS are the strobe signals for DQ0 to DQ7 and
DQ8 to DQ15, respectively.
2.24
LPSDRAM VDDD supply voltage
VDDD provides the power supply to the internal core of the LPSDRAM. It is the main power
supply for all operations (read and write).
2.25
LPSDRAM VDDQD supply voltage
VDDQD provides the power supply to the I/O pins of the LPSDRAM and enables all outputs
to be powered independently of VDDD. VDDQD can be tied to VDDD or can use a separate
supply.
It is recommended to power-up and power-down VDDD and VDDQD together to avoid certain
conditions that would result in data corruption.
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| NANDBAR4N2AZBA5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
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