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參數(shù)資料
| 型號(hào)： | MT9076 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 3.3V Single Chip Transceiver |
| 中文描述： | T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器 |
| 文件頁(yè)數(shù)： | 63/160頁(yè) |
| 文件大?。?/td> | 416K |
| 代理商： | MT9076 |
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Preliminary Information
MT9076
59
Bit
Name
Functional Description
7
ESF
Extended Super Frame
. Setting this bit enables transmission and reception of the 24 frame
superframe DS1 protocol.
6
SLC96
SLC96 Mode Select
. Setting this bit enables input and output of the Fs bit pattern on the TxDL
and RxDL pins. Frame synchronization is the same as in the case of D4 operation. The
transmitter will insert A and B bits every 6 frames after synchronizing to the Fs pattern clocked
into Txdl. Receive Fs bits are not monitored for the Framing Bit Error Counter.
5
CXC
Cross Check
. Setting this bit in ESF mode enables a cross check of the CRC-6 remainder
before the frame synchronizer pulls into sync. This process adds at least 6 milliseconds to the
frame synchronization time. Setting this bit in D4 (not ESF) mode enables a check of the Fs
bits in addition to the Ft bits during frame synchronization
4 - 3
RS1- 0
Reframe Select 1 - 0
. These bits set the criteria for an automatic reframe in the event of
framing bits errors. The combinations available are:
RS1 - 0, RS0 - 0 = sliding window of 2 errors out of 4.
RS1 - 0, RS0 - 1 = sliding window of 2 errors out of 5.
RS1 - 1, RS0 - 0 = sliding window of 2 errors out of 6.
RS1 - 1, RS0 - 1 = no reframes due to framing bit errors.
2
FSI
Fs Bit Include
. Only applicable in D4 mode (not ESF or SLC96). Setting this bit causes
errored Fs bits to be included as framing bit errors. A bad Fs bit will increment the Framing
Error Bit Counter, and will potentially cause a reframe (if it is the second bad framing bit out of
5). The Fs bit of the receive frame 12 will only be included if D4SECY is set.
1
ReFR
Reframe
. A low - to - high transition on this bit causes an automatic reframe.
0
MFReFR
MultiFrame Reframe
. Only applicable in D4 or SLC96 mode. A low - to - high transition on this
bit causes an automatic multiframe reframe. The signaling bits are frozen until multiframe
synchronization is achieved. Terminal frame synchronization is not affected.
Table 21 - Framing Mode Select (T1)
(Page 1, Address 10H)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9076AB | T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| MT9079 | Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器) |
| MT9080B | SMX - Switch Matrix Module(用于消費(fèi)類(lèi)轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊) |
| MT90810 | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9076AB | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076AP | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076B | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
| MT9076BB | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BB1 | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
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