
Preliminary Information
MT9076
15
Maskable Interrupts
T1/J1 Mode
E1 Mode
HDLC Interrupts
Change of state of terminal
synchronization
Change of state of multiframe
synchronization
Change of received bit
oriented message
Change of state of reception
of AIS
Change of state of reception
of LOS
Reception of a severely
errored frame
Transmit slip
Receive slip
Receive framing bit error
Receive CRC-6 error
Receive yellow alarm
Change of receive frame
alignment
Receive line code violation
Receive PRBS error
Pulse density violation
Framing bit error counter
overflow
CRC-6 error counter overflow
Out of frame alignment
counter overflow
Change of frame alignment
counter overflow
Line code violation counter
overflow
PRBS error counter overflow
PRBS multiframe counter
overflow
Multiframes out of alignment
counter overflow
Loop code detected
One second timer
Five second timer
Receive new bit oriented
message (debounced)
Signaling (AB or ABCD) bit
change
Change of state of basic
frame alignment
Change of state of multiframe
synchronization
Change of state of CRC-4
multiframe synchronization
Change of state of reception
of AIS
Change of state of reception
of LOS
Reception of consecutively
errored FASs
Receive remote signaling
multiframe alarm
Receive slip
Receive FAS error
Receive CRC-4 error
Receive E-bit
Receive AIS in timeslot 16
Line code violation
Receive PRBS error
Receive auxiliary pattern
Receive RAI
FAS error counter overflow
CRC-4 error counter overflow
Out of frame alignment
counter overflow
Receive E-bit counter
overflow
Line code violation counter
overflow
PRBS error counter overflow
PRBS multiframe counter
overflow
Change of state of any Sa bit
or Sa nibble
Jitter attenuator within 4 bits
of overflow/underflow
One second timer
Two second timer
Signaling (CAS) bit change
Go ahead pattern received
End of packet received
End of packet transmitted
End of packet read from
receive FIFO
Transmit FIFO low
Frame abort received
Transmit FIFO underrun
Receive FIFO full
Receive FIFO overflow