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參數(shù)資料
| 型號(hào)： | MT9076 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 3.3V Single Chip Transceiver |
| 中文描述： | T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器 |
| 文件頁(yè)數(shù)： | 46/160頁(yè) |
| 文件大小： | 416K |
| 代理商： | MT9076 |
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MT9076
Preliminary Information
42
Figure 13 - Read and Write Pointers in the Transmit Slip Buffers
The RSLIP and RSLPD status bits (page 3H, address 13H, bits 7 and 6 respectively) give indication of a
receive slip occurance and direction. A maskable interrupt RxSLPI (page 1H, address 1BH, bit 0 - set high to
mask) is also provided. RSLIP changes state in the event of a slip. If RSLPD=0, the slip buffer has overflowed
and a frame was lost; if RSLPD=1, a underflow condition occurred and a frame was repeated.
9.2
Slip Buffer in E1 mode
In E1 mode, in addition to the elastic buffer in the jitter attenuator(JA), another elastic buffer (two frames deep)
is present, attached between the receive side and the ST-BUS side of the MT9076. This elastic buffer is
configured as a slip buffer which absorbs wander and low frequency jitter in multi-trunk applications. The
received PCM 30 data is clocked into the slip buffer with the Exclk clock and is clocked out of the slip buffer with
the C4b clock. The Exclk extracted clock is generated from, and is therefore phase-locked with, the receive
PCM 30 data. In normal operation, the C4b clock will be phase-locked to the Exclk clock by a phase locked loop
(PLL). Therefore, in a single trunk system the receive data is in phase with the Exclk clock, the C4b clock is
phase-locked to the Exclk clock, and the read and write positions of the slip buffer will remain fixed with respect
to each other.
In a multi-trunk slave or loop-timed system (i.e., PABX application) a single trunk will be chosen as a network
synchronizer, which will function as described in the previous paragraph. The remaining trunks will use the
system timing derived from the synchronizer to clock data out of their slip buffers. Even though the PCM 30
signals from the network are synchronous to each other, due to multiplexing, transmission impairments and
route diversity, these signals may jitter or wander with respect to the synchronizing trunk signal. Therefore, the
Exclk clocks of non-synchronizer trunks may wander with respect to the Exclk clock of the synchronizer and the
system bus.
Network standards state that, within limits, trunk interfaces must be able to receive error-free data in the
presence of jitter and wander (refer to network requirements for jitter and wander tolerance). The MT9076 will
allow a maximum of 26 channels (208 UI, unit intervals) of wander and low frequency jitter before a frame slip
will occur.
Write
Pointer
221 uS
4 uS
188 uS
62 uS
129 uS
512 Bit
Elastic
Store
92 uS
92 uS
Wander Tolerance
Read Pointer
Read Pointer
Read Pointer
Read Pointer
0 uS
Frame 0
Frame 1
Frame 0
Frame 1
Frame 0
Frame 1
Write Vectors
Read Vectors
Minimum Delay
Read Vectors - Maximum Delay
96 uS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9076AB | T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| MT9079 | Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器) |
| MT9080B | SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊) |
| MT90810 | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9076AB | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
| MT9076BB | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BB1 | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
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