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參數(shù)資料
| 型號(hào)： | MT9076 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | T1/E1/J1 3.3V Single Chip Transceiver |
| 中文描述： | T1/E1/J1收發(fā)3.3V的單芯片收發(fā)器 |
| 文件頁(yè)數(shù)： | 40/160頁(yè) |
| 文件大?。?/td> | 416K |
| 代理商： | MT9076 |
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MT9076
Preliminary Information
36
8.2
HDLC Description
The HDLC handles the bit oriented packetized data transmission as per X.25 level two protocol defined by
CCITT. It provides flag and abort sequence generation and detection, zero insertion and deletion, and Frame
Check Sequence (FCS) generation and detection. A single byte, dual byte and all call address in the received
frame can be recognized. Access to the receive FCS and inhibiting of transmit FCS for terminal adaptation are
also provided. Each HDLC controller has a 128 byte deep FIFO associated with it. The status and interrupt
flags are programmable for FIFO depths that can vary from 16 to 128 bytes in steps of 16 bytes. These and
other features are enabled through the HDLC control registers on page 0BH and 0CH.
8.2.1
In T1 mode or E1 mode, a valid HDLC frame begins with an opening flag, contains at least 16 bits of address
and control or information, and ends with a 16 bit FCS followed by a closing flag. Data formatted in this manner
is also referred to as a “packet”. Refer to Table 17: HDLC Frame Format
HDLC Frame structure
All HDLC frames start and end with a unique flag sequence “01111110”. The transmitter generates these flags
and appends them to the packet to be transmitted. The receiver searches the incoming data stream for the
flags on a bit- by-bit basis to establish frame synchronization.
The data field consists of an address field, control field and information field. The address field consists of one
or two bytes directly following the opening flag. The control field consists of one byte directly following the
address field. The information field immediately follows the control field and consists of N bytes of data. The
HDLC does not distinguish between the control and information fields and a packet does not need to contain an
information field to be valid.
The FCS field, which precedes the closing flag, consists of two bytes. A cyclic redundancy check utilizing the
CRC-CCITT standard generator polynomial “X
16
+X
12
+X
5
+1” produces the 16-bit FCS. In the transmitter the
FCS is calculated on all bits of the address and data field. The complement of the FCS is transmitted, most
significant bit first, in the FCS field. The receiver calculates the FCS on the incoming packet address, data and
FCS field and compares the result to “F0B8”. If no transmission errors are detected and the packet between the
flags is at least 32 bits in length then the address and data are entered into the receive FIFO minus the FCS
which is discarded.
8.2.2
Transparency ensures that the contents of a data packet do not imitate a flag, go-ahead, frame abort or idle
channel. The contents of a transmitted frame, between the flags, is examined on a bit-by-bit basis and a 0 bit is
inserted after all sequences of 5 contiguous 1 bits (including the last five bits of the FCS). Upon receiving five
contiguous 1s within a frame the receiver deletes the following 0 bit.
Data Transparency (Zero Insertion/Deletion)
8.2.3
A frame is invalid if one of the following four conditions exists (Inserted zeros are not part of a valid count):
If the FCS pattern generated from the received data does not match the “F0B8” pattern then the last
data byte of the packet is written to the received FIFO with a ‘bad packet’ indication.
A short frame exists if there are less than 25 bits between the flags. Short frames are ignored by the
receiver and nothing is written to the receive FIFO.
Packets which are at least 25 bits in length but less than 32 bits between the flags are also invalid. In
this case the data is written to the FIFO but the last byte is tagged with a “bad packet” indication.
If a frame abort sequence is detected the packet is invalid. Some or all of the current packet will reside
in the receive FIFO, assuming the packet length before the abort sequence was at least 26 bits long.
Invalid Frames
Flag (7E)
Data Field
FCS
Flag (7E)
One Byte
01111110
n Bytes
n
≥
2
Two Bytes
One Byte
01111110
Table 17 - HDLC Frame Format
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9076AB | T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076 | T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 單片收發(fā)器) |
| MT9079 | Advanced Controller for E1(先進(jìn)的E1幀調(diào)節(jié)器和控制器) |
| MT9080B | SMX - Switch Matrix Module(用于消費(fèi)類轉(zhuǎn)換應(yīng)用的開(kāi)關(guān)矩陣模塊) |
| MT90810 | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9076AB | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/E1/J1 3.3V Single Chip Transceiver |
| MT9076B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 3.3 V Single Chip Transceiver |
| MT9076BB | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
| MT9076BB1 | 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 3.3V 80LQFP - Trays |
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