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參數(shù)資料
| 型號： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲器) |
| 中文描述： | 2梅格× 8 /檢測起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲器） |
| 文件頁數(shù)： | 35/39頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MT28F160S3 |
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35
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
AC CHARACTERISTICS – WRITE OPERATIONS
Notes: 1, 2; Commercial Temperature (0oC
≤
T
A
≤
+70oC) and Extended Temperature (-40oC
≤
T
A
≤
+85oC)
3.3V ±0.3V V
CC
-75
MIN
1
10
0
50
70
50
50
10
0
5
5
30
25
100
100
0
2.7V–3.6V V
CC
-10
MIN
1
10
0
50
70
50
50
10
0
5
5
25
25
100
100
0
PARAMETER
RP# HIGH Recovery to WE# (CEx#) Going LOW
CEx# Setup to WE# Going LOW
WE# Setup to CEx# Going LOW
WE# Pulse Width
CEx# Pulse Width
Data Setup to WE# (CEx#) Going HIGH
Address Setup to WE# (CEx#) Going HIGH
CEx# Hold from WE# HIGH
WE# Hold from CEx# HIGH
Data Hold from WE# (CEx#) HIGH
Address Hold from WE# (CEx#) HIGH
Pulse Width HIGH
CEx# Pulse Width HIGH
WP# V
IH
Setup to WE# (CEx#) Going HIGH
V
PP
Setup to WE# (CEx#) Going HIGH
Write Recovery before READ
WE# HIGH to STS in RY/BY# LOW
WE# (CEx#) HIGH to Busy Status (SR7 = 0)
WP# V
IH
Hold from Valid SRD
V
PP
Hold from Valid SRD, STS in RY#/BY# HIGH
SYMBOL
t
RS
t
CS
t
WS
t
WP
t
CP
t
DS
t
AS
t
CH
t
WH
t
DH
t
AH
t
WPH
t
CPH
t
WPS
t
VPS
t
WR
t
STS
t
WB
t
QVSL
t
VPH
MAX
MAX
UNITS
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
3
4
4
3
100
100
100
100
3, 5
3, 5
3, 5
0
0
0
0
NOTE:
1. READ timing characteristics during BLOCK ERASE, PROGRAM, and LOCK BIT CONFIGURATION operations are the same as
during READ-only operations. Refer to AC Characteristics – READ-Only Operations.
2. See READ, WRITE, and RESET timing diagrams for testing characteristics.
3. Sampled, not 100% tested.
4. Refer to Table 2 for valid A
IN
and D
IN
for block erase, program, or lock bit configuration.
5. V
PP
should be at V
PPH
1/2/3
until determination of block erase, program, or lock bit configuration success (SR1/3/4/5 = 0).
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