- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384755 > MT28F160S3 (Micron Technology, Inc.) 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲器) PDF資料下載
參數(shù)資料
| 型號： | MT28F160S3 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 Meg x 8/1 Meg x 16 Smart 3 Flash(2 M x 8/1 M x 16閃速存儲器) |
| 中文描述： | 2梅格× 8 /檢測起× 16智能3閃光（2 M中的x 8月1日M中的x 16閃速存儲器） |
| 文件頁數(shù)： | 16/39頁 |
| 文件大?。?/td> | 281K |
| 代理商： | MT28F160S3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
16
2 Meg x 8 /1 Meg x 16 Even-Sectored Flash Memory
MT28F160S3_2 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2 MEG x 8/1 MEG x 16
SMART 3 EVEN-SECTORED FLASH
PRELIMINARY
This two-step command sequence of setup followed
by execution ensures that block contents are not acci-
dentally erased. An invalid block erase command se-
quence will result in both status register bits SR4 and SR5
being set to “1.” Also, reliable block erasure can only
occur when V
CC
= V
CC
1/2
and V
PP
= V
PPH
1/2/3
. In the
absence of these voltages, block contents are protected
against erasure. If BLOCK ERASE is attempted while V
PP
≤
V
PPLK
, SR3 and SR5 will be set to “1.” Successful BLOCK
ERASE requires that the corresponding block lock bit be
cleared or that WP#
V
IH
. If BLOCK ERASE is attempted
when the corresponding block lock bit is set and WP#
= V
IL
, the BLOCK ERASE will fail, and SR1 and SR5 will
be set to “1.”
FULL CHIP ERASE COMMAND
The FULL CHIP ERASE command erases all un-
locked blocks. After the CONFIRM command is writ-
ten, the device erases all unlocked blocks from block 0
to block 31 sequentially. Block preconditioning, erase,
and verify are handled internally by the ISM. After the
full chip erase command sequence is written to the CEL,
the device automatically outputs the status register
data when read. The CPU can detect full chip erase
completion by polling the STS pin in RY/BY# level mode
or status register bit SR7.
Once the FULL CHIP ERASE is complete, status
register bit SR5 should be checked to see if the operation
completed successfully. If an erase error occurred, the
status register should be cleared before issuing the next
command. The CEL remains in read status register mode
until a new command is issued. In the absence of these
voltages, the block contents can be protected against
erasure. Issuing the READ IDENTIFIER CODES com-
mand or QUERY command can inform the user of
which block(s) failed to erase. This two-step command
sequence of setup followed by execution ensures that
block contents are not accidentally erased. An invalid
full chip erase command sequence will set both status
register bits SR4 and SR5 to “1.” Also, reliable full chip
erasure can only occur when V
CC
= V
CC
1/2
and V
PP
=
V
PPH
1/2/3
. Block contents can be protected against era-
sure in the absence of these voltages. If FULL CHIP
ERASE is attempted while V
PP
≤
V
PPLK
, SR3 and SR5 will
be set to “1.” FULL CHIP ERASE cannot be suspended.
WRITE-TO-BUFFER COMMAND
A WRITE-to-BUFFER command sequence is initi-
ated to program the flash device via the write buffer. A
variable number of bytes or words can be written into
the buffer and be programmed to the flash device. First,
the WRITE-to-BUFFER SETUP command is issued,
along with the block address. At this point, the X SR
information is loaded and X SR7 indicates that another
WRITE-to-BUFFER command is possible. If X SR7 = 0,
the write buffer is not available. To retry, continue
monitoring X SR7 by issuing the WRITE-to-BUFFER
SETUP command with the block address until X SR7 =
1. When X SR7 = 1, the buffer is ready for loading. Next,
a word or byte count is issued at a valid address within
the block. On the next write, a device start address is
given along with the write buffer data. To optimize the
performance and lower power, align the start address
at the beginning of a write buffer boundary. Depending
on the count, subsequent writes must supply addi-
tional device addresses and data.
Once the final buffer data is given, a WRITE CON-
FIRM command is issued. This allows the ISM to begin
copying the buffer data to the flash memory. If a
command other than WRITE CONFIRM is written to
the device, an invalid command/sequence error will be
generated and status register bits SR5 and SR4 will be set
to “1.” Additional BUFFER WRITEs can be issued with
another WRITE-to-BUFFER SETUP command and check
X SR7. Refer to Figure 3 for the WRITE-to-BUFFER
Flowchart.
If an error occurs during writing, the device will stop
programming, and status register bit SR4 will be set to
a “1” to indicate a program failure. Any time a media
failure occurs during a program or erase (SR4 or SR5 is
set), the device will not accept any more WRITE-to-
BUFFER commands. Additionally, if the user attempts
to write past an erase block boundary with a WRITE-
to-BUFFER command, the device will abort program-
ming and generate an invalid command/sequence
error, and status register bits SR5 and SR4 will be set to
“1.” To clear SR4 and/or SR5, issue a CLEAR STATUS
REGISTER command. Buffered programming can only
occur when V
CC
= V
CC
1/2
and V
PP
= V
PPH
1/2/3
. If program-
ming is attempted while V
PP
≤
V
PPLK
, status register bits
SR4 and SR5 will be set to “1.” Programming attempts
with invalid V
CC
and V
PP
voltages produce spurious
results and should not be attempted. Finally, successful
programming requires that the corresponding block
lock bit be cleared, or WP# = V
IH
. If a BUFFER WRITE
command is issued when the corresponding block lock
bit is set and WP# = V
IL
, SR1 and SR4 will be set to “1.”
BYTE/WORD PROGRAM COMMANDS
The byte/word programming is executed by a two-
cycle command sequence. After the byte/word pro-
gram setup, a second write is needed to specify the
address and data (latched on the rising edge of WE#).
Next, the ISM takes over to control the program and
verify algorithms internally. Once the write sequence is
written, the device automatically outputs status register
data when read. The CPU can detect the completion of
the program event by analyzing the STS in RY/BY# level
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT28F640J3 | 64Mb Flash Memory(64Mb閃速存儲器) |
| MT35212A | BELL 212A/CCITT V.22 Modem Filter |
| MT35212AE | BELL 212A/CCITT V.22 Modem Filter |
| MT35212AP | BELL 212A/CCITT V.22 Modem Filter |
| MT46V32M16TG-8L | DOUBLE DATA RATE DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT28F200B3 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:FLASH MEMORY |
| MT28F200B5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:FLASH MEMORY |
| MT28F200B5SG-6 B | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-6 T | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 5V 2Mbit 256K/128K x 8bit/16bit 60ns 44-Pin SOP Tray |
| MT28F200B5SG-8 B TR | 制造商:Micron Technology Inc 功能描述:Flash Mem Parallel 5V 2M-Bit 256K x 8/128K x 16 80ns 44-Pin SOP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。