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參數(shù)資料
| 型號： | MSC8103M1200F |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 75 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 57/104頁 |
| 文件大?。?/td> | 1810K |
| 代理商： | MSC8103M1200F |
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MSC8103 Network Digital Signal Processor, Rev. 11
2-16
Freescale Semiconductor
Physical and Electrical Specifications
Table 2-17.
AC Timing for SIU Outputs
No.
Characteristic
Min.
Maximum2
Units
30 pF
50 pF
31a
TA delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
5.0
4.0
6.5
5.5
ns
31b
TEA delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
3.0
3.5
4.5
5.0
ns
31c
PSDVAL delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
4.0
3.5
5.5
5.0
ns
32a
Address bus delay from the 50% level of the DLLIN rising edge
Multi master mode (SIUBCR[EBM] = 1)
Single master mode (SIUBCR[EBM] = 0)
1.0
6.3
5.5
7.8
7.0
ns
32b
Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the DLLIN rising edge
1.0
5.5
7.0
ns
32c
BADDR delay from the 50% level of the DLLIN rising edge
1.0
3.5
5.0
ns
33a
Data bus delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
5.0
6.0
6.5
7.5
ns
33b
DP delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
4.0
6.5
5.5
8.0
ns
34
Memory controller signals/ALE delay from the 50% level of the DLLIN rising edge
1.0
5.5
7.0
ns
35a
DBG/BR/DBB delay from the 50% level of the DLLIN rising edge
1.0
4.0
5.5
ns
35b
AACK/ABB/CS delay from the 50% level of the DLLIN rising edge
1.0
4.5
6.0
ns
35c
BG delay from the 50% level of the DLLIN rising edge
1.0
4.0
5.5
ns
35d
TS delay from the 50% level of the DLLIN rising edge
1.0
3.5
5.0
ns
36
Delay from the 50% level of the DLLIN rising edge for all other signals
1.0
4.5
6.0
ns
Notes:
1.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8103 device, the frequency is determined by adding the input and output
longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when
connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values,
which results in a frequency of 75 MHz for 30 pF output capacitance.
Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus
frequencies.
In single-master mode, the frequency depends on the timing of the devices connected to the MSC8103.
2.
Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
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