參數(shù)資料
型號: MSC8103M1200F
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù): 28/104頁
文件大?。?/td> 1810K
代理商: MSC8103M1200F
MSC8103 Network Digital Signal Processor, Rev. 11
Freescale Semiconductor
iii
MSC8103 Features
SC140 core
— Architecture optimized for efficient C/C++ code compilation
— Four 16-bit ALUs and two 32-bit AGUs
— 1200 DSP MMACS running at 300 MHz
— Very low power dissipation
— Variable-length execution set (VLES) execution model
— JTAG/Enhanced OnCE debug port
Communications processor module (CPM)
— Programmable protocol machine using a 32-bit RISC engine
— 155 Mbps ATM interface (including AAL 0/1/2/5)
— 10/100 Mbit Ethernet interface
— Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface
— HDLC support up to T3 rates, or 256 channels
64- or 32-bit wide bus interface
— Support for bursts for high efficiency
— Glueless interface to 60x-compatible bus systems
— Multi-master support
Programmable memory controller
— Control for up to eight banks of external memory
— User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM,
EPROM, and Flash memory) and other user-definable peripherals
— Dedicated pipelined SDRAM memory interface
Large internal SRAM
— 256K 16-bit words (512 KB)
— Unified program and data space configurable by the application
— Word and byte addressable
DMA controller
— 16 DMA channels, FIFO based, with burst capabilities
— Sophisticated addressing capabilities
Small foot print package
—17 mm
× 17 mm lidded FC-PBGA package with lead-bearing or lead-free spheres
Very low power consumption
— Separate power supply for internal logic (1.6 V) and for I/O (3.3 V)
Enhanced 16-bit parallel host interface (HDI16)
— Supports a variety of microcontroller, microprocessor, and DSP bus interfaces
Phase-lock loops (PLLs)
—System PLL
— CPM DPLLs (SCC and SCM)
Process technology
— 0.13 micron copper interconnect process technology
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