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參數(shù)資料
| 型號： | MSC8103M1200F |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 75 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 20/104頁 |
| 文件大?。?/td> | 1810K |
| 代理商： | MSC8103M1200F |
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MSC8103 Network Digital Signal Processor, Rev. 11
1-18
Freescale Semiconductor
Signals/Connections
PA22
FCC1: TXD3
UTOPIA
Output
FCC1: UTOPIA Transmit Data Bit 3
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 3 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
PA21
FCC1: TXD4
UTOPIA
FCC1: TXD3
MII and HDLC nibble
Output
FCC1: UTOPIA Transmit Data Bit 4
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 4 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 3
TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the
most significant bit.
PA20
FCC1: TXD5
UTOPIA
FCC1: TXD2
MII and HDLC nibble
Output
FCC1: UTOPIA Transmit Data Bit 5
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. This is bit 5 of the transmit data. TXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 2
TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. This is
bit 2 of the transmit data. TXD3 is the most significant bit.
PA19
FCC1: TXD6
UTOPIA
FCC1: TXD1
MII and HDLC nibble
Output
FCC1: UTOPIA Transmit Data Bit 6
The MSC8103MSC8103 outputs ATM cell octets (UTOPIA interface
data) on TXD[0–7]. This is bit 6 of the transmit data. TXD7 is the most
significant bit. When no ATM data is available, idle cells are inserted. A
cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 1
TXD[3–0] is supported by MII and HDLC transparent nibble modes in
FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit.
PA18
FCC1: TXD7
UTOPIA
FCC1: TXD0
MII and HDLC nibble
FCC1: TXD
HDLC serial and transparent
Output
FCC1: UTOPIA Transmit Data Bit 7.
The MSC8103 outputs ATM cell octets (UTOPIA interface data) on
TXD[0–7]. TXD7 is the most significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 0
TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. TXD0
is the least significant bit.
FCC1: HDLC Serial and Transparent Transmit Data Bit
This is the single transmit data bit in supported by HDLC serial and
transparent modes.
Table 1-7.
Port A Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated Signal
Protocol
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MSC8103RM/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
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| MSC8103VT1200F | 功能描述:IC DSP 16BIT 300MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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