參數(shù)資料
型號(hào): MSC8103M1200F
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù): 45/104頁(yè)
文件大?。?/td> 1810K
代理商: MSC8103M1200F
Clock Configuration
MSC8103 Network Digital Signal Processor, Rev. 11
Freescale Semiconductor
2-5
2.5.2.1 System Clock Control Register
SCCR is memory-mapped into the SIU register map of the MSC8103.
2.5.2.2 System Clock Mode Register
SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control
signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For
details of the available setting options, see AN2306/D.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Type
Reserved
Reset
Bit
1617
1819
2021
2223
2425
262728293031
CLKODIS
—DFBRG
Type
Reserved
R/W
Reserved
R/W
Reset
0
0
1
Figure 2-2.
System Clock Control Register (SCCR)—0x10C80
Table 2-7.
SCCR Bit Descriptions
Name
Bit No.
Defaults
Description
Settings
PORESET
Hard Reset
0–26
Reserved. Write to 0 fro future compatibility.
CLKODIS
27
0
Unaffected
CLKOUT Disable
Disables the CLKOUT signal. The value of
CLKOUT when disabled is indeterminate (can be 1
or 0).
0
CLKOUT enabled (default)
1
CLKOUT disabled
28–29
Reserved. Write to 0 fro future compatibility.
DFBRG
30–31
01
Unaffected
Division Factor for the BRG Clock Defines the
BRGCLK frequency. Changing this value does not
result in a loss of lock condition.
00
Divide by 4
01
Divide by 16 (default value)
10
Divide by 64
11
Divide by 256
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COREPDF
COREMF
BUSDF
CPMDF
Type
R
Reset
Bit
1617
1819
2021
2223
2425
262728293031
SPLLPDF
SPLLMF
DLLDIS
COREDF
Type
R
Reset
Figure 2-3.
System Clock Mode Register (SCMR)—0x10C88
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