參數(shù)資料
型號： MSC8103M1200F
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù)： 23/104頁
文件大?。?/td> 1810K
代理商： MSC8103M1200F
CPM Ports
MSC8103 Network Digital Signal Processor, Rev. 11
Freescale Semiconductor
1-21
1.6.2
Port B Signals
PA7
SMC2: SMSYN
SI1 TDMA1: L1TSYNC
TDM nibble and TDM serial
Input
SMC2: Serial Management Synchronization
The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock.
Not all signals are used for all applications. SMCs are full-duplex ports
that supports three protocols or modes: UART, transparent, or general-
circuit interface (GCI).
Time-Division Multiplexing A1: Layer 1 Transmit Synchronization
The synchronizing signal for the transmit channel. See the
Serial
Interface with time-slot assigner chapter in the MSC8103 Reference
Manual.
PA6
SI1 TDMA1: L1RSYNC
TDM nibble and TDM serial
Input
Time-Division Multiplexing A1: Layer 1 Receive Synchronization.
The synchronizing signal for the receive channel.
Table 1-8.
Port B Signals
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
PB31
FCC2: TX_ER
MII
SCC2: RXD
SI2 TDMB2: L1TXD
TDM serial
Output
Input
Output
FCC2: Media Independent Interface Transmit Error
Asserted by the MSC8103 to force propagation of transmit errors.
SCC2: Receive Data
SCC2 receives serial data from RXD.
Time-Division Multiplexing B2: Layer 1 Transmit Data
TDMB2 transmits serial data out of L1TXD.
PB30
SCC2: TXD
FCC2: RX_DV
MII
SI2 TDMB2: L1RXD
TDM serial
Output
Input
SCC2: Transmit Data.
SCC2 transmits serial data out of TXD.
FCC2: Media Independent Interface Receive Data Valid
Asserted by an external fast Ethernet PHY to indicate that valid data is
being sent. The presence of carrier sense, but not RX_DV, indicates
reception of broken packet headers, probably due to bad wiring or a bad
circuit.
Time-Division Multiplexing B2: Layer 1 Receive Data
TDMB2 receives serial data from L1RXD.
PB29
FCC2: TX_EN
MII
SI2 TDMB2: L1RSYNC
TDM serial
Output
Input
FCC2: Media Independent Interface Transmit Enable
Asserted by the MSC8103 when transmitting data.
Time-Division Multiplexing B2: Layer 1 Receive Synchronization
The synchronizing signal for the receive channel.
Table 1-7.
Port A Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated Signal
Protocol
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