參數(shù)資料
型號(hào): MSC8103M1200F
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù): 104/104頁(yè)
文件大?。?/td> 1810K
代理商: MSC8103M1200F
MSC8103 Network Digital Signal Processor, Rev. 11
Freescale Semiconductor
4-1
Design Considerations
4
This chapter includes design and layout guidelines for manufacturing boards using the MSC8103.
4.1 Thermal Design Considerations
The average chip-junction temperature, TJ, in ° C can be obtained from the following:
TJ = TA + (PD θJA)
Equation 1
where
TA = ambient temperature ° C
θ
JA = package thermal resistance, junction to ambient, ° C/W
PD = PINT + PI/O in W
PINT = IDD × VDD in W—chip internal power
PI/O = power dissipation on output pins in W—user determined
The user should set TA and PD such that TJ does not exceed the maximum operating conditions. In case TJ is too
high, the user should either lower the ambient temperature or the power dissipation of the chip.
The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on
reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms.
VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH
by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use
“bootstrap” diodes between the power rails, as shown in Figure 4-1.
Figure 4-1.
Bootstrap Diodes for Power-Up Sequencing
I/O Power
Core/PLL
Supply
MUR420
3.3 V (VDDH)
1.6 V (VDD/VCCSYN)
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