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參數(shù)資料
| 型號： | MQ80C154-16P883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 93/142頁 |
| 文件大小： | 61013K |
| 代理商： | MQ80C154-16P883 |
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182
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Referring to the timing diagram (Figure 21-5 on page 181), a bus transfer involves the following steps:
1.
The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A).
SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding
bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output
to be enabled. The slave device’s start detector logic (Figure 21-6 on page 182) detects the start condition
and sets the USISIF Flag. The flag can generate an interrupt if necessary.
2.
In addition, the start detector will hold the SCL line low after the Master has forced an negative edge on this
line (B). This allows the Slave to wake up from sleep or complete its other tasks before setting up the Shift
Register to receive the address. This is done by clearing the start condition flag and reset the counter.
3.
The Master set the first bit to be transferred and releases the SCL line (C). The Slave samples the data and
shift it into the Serial Register at the positive edge of the SCL clock.
4.
After eight bits are transferred containing slave address and data direction (read or write), the Slave counter
overflows and the SCL line is forced low (D). If the slave is not the one the Master has addressed, it
releases the SCL line and waits for a new start condition.
5.
If the Slave is addressed it holds the SDA line low during the acknowledgment cycle before holding the SCL
line low again (i.e., the Counter Register must be set to 14 before releasing SCL at (D)). Depending of the
R/W bit the Master or Slave enables its output. If the bit is set, a master read operation is in progress (i.e.,
the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
6.
Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the Master (F).
Or a new start condition is given.
If the Slave is not able to receive more data it does not acknowledge the data byte it has last received. When the
Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte
transmitted.
Figure 21-6. Start Condition Detector, logic diagram.
21.3.5
Start Condition Detector
The start condition detector is shown in Figure 21-6. The SDA line is delayed (in the range of 50 to 300ns) to
ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the processor from the Power-
down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when
using this feature in this case the Oscillator start-up time set by the CKSEL Fuses (see ”Clock systems and their
distribution” on page 27) must also be taken into the consideration. Refer to the USISIF bit description on page 184
for further details.
21.3.6
Clock speed considerations.
Maximum frequency for SCL and SCK is f_CK /4. This is also the maximum data transmit and receieve rate in both
two- and three-wire mode. In two-wire slave mode the Two-wire Clock Control Unit will hold the SCL low until the
slave is ready to receive more data. This may reduce the actual data rate in two-wire mode.
21.4
Alternative USI Usage
When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible
design.
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
DQ
CLR
DQ
CLR
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| MQ83C154XXX-L16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MQ83C154CXXX-25/883R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MR80C154-L16/883R | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ83C154CXXX-L16P883R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MQ80C154-20 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-25 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-30 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-36 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-L16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
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