參數(shù)資料
型號(hào)： MQ80C154-16P883
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù)： 22/142頁
文件大?。?/td> 61013K
代理商： MQ80C154-16P883
118
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Table 16-4 shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the phase correct or the
phase and frequency correct, PWM mode.
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See ”Phase Correct PWM
Mode” on page 111. for more details.
Bit 1:0 – WGM1[1:0]: Waveform Generation Mode
Combined with the WGM1[3:2] bits found in the TCCR1B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 16-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See ”Modes of Opera-
Table 16-4.
Compare Output Mode, phase correct and phase and frequency correct PWM
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
01
WGM1[3:0] = 9 or 11: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings, normal
port operation, OC1A/OC1B disconnected.
10
Clear OC1A/OC1B on Compare Match when up-counting. Set
OC1A/OC1B on Compare Match when down counting.
11
Set OC1A/OC1B on Compare Match when up-counting. Clear
OC1A/OC1B on Compare Match when down counting.
相關(guān)PDF資料
PDF描述
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