參數(shù)資料
型號: MQ80C154-16P883
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù): 137/142頁
文件大?。?/td> 61013K
代理商: MQ80C154-16P883
221
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
25.5.3
Scanning the Clock Pins
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock,
(High Frequency) XTAL Oscillator, Low-frequency XTAL Oscillator, and Ceramic Resonator.
Figure 25-6 on page 221 shows how each Oscillator with external connection is supported in the scan chain. The
Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an
observe-only cell. In addition to the main clock, the timer Oscillator is scanned in the same way. The output from
the internal RC Oscillator is not scanned, as this Oscillator does not have external connections.
Figure 25-6. Boundary-scan cells for oscillators and Clock options.
Table 25-1 on page 221 summaries the scan registers for the external clock pin XTAL1, oscillators with
XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator.
Notes:
1. Do not enable more than one clock source as main clock at a time.
2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the internal Oscilla-
tor and the JTAG TCK clock. If possible, scanning an external clock is preferred.
3. The clock configuration is programmed by fuses. As a fuse is not changed run-time, the clock configuration is con-
sidered fixed for a given application. The user is advised to scan the same clock option as to be used in the final
system. The enable signals are supported in the scan chain because the system logic can disable clock options in
sleep modes, thereby disconnecting the Oscillator pins from the scan path if not provided.
25.5.4
Scanning the Analog Comparator
The relevant Comparator signals regarding Boundary-scan are shown in Figure 25-7 on page 222. The Boundary-
scan cell from Figure 25-8 on page 222 is attached to each of these signals. The signals are described in Table 25-
The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital
port pin as well.
Table 25-1.
Scan signals for the oscillator
Enable signal
Scanned Clock Line
Clock option
Scanned Clock Line when not used
EXTCLKEN
EXTCLK (XTAL1)
External Clock
0
OSCON
OSCCK
External XTAL
External Ceramic Resonator
1
OSC32EN
OSC32CK
Low Freq. External XTAL
1
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
To System Logic
FF1
0
1
DQ
G
0
1
From
Previous
Cell
ClockDR
UpdateDR
ShiftDR
To
Next
Cell
EXTEST
From Digital Logic
XTAL1/TOSC1
XTAL2/TOSC2
Oscillator
ENABLE
OUTPUT
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