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參數(shù)資料
| 型號： | MQ80C154-16P883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 63/142頁 |
| 文件大小： | 61013K |
| 代理商： | MQ80C154-16P883 |
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155
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
20.3.4
Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock
output (Master). The dependency between the clock edges and data sampling or data change is the same. The
basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output
(TxD) is changed.
Figure 20-3. Synchronous mode XCK timing.
The UCPOLn bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data
change. As Figure 20-3 shows, when UCPOLn is zero the data will be changed at rising XCK edge and sampled at
falling XCK edge. If UCPOLn is set, the data will be changed at falling XCK edge and sampled at rising XCK edge.
20.4
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and option-
ally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats:
1 start bit
5, 6, 7, 8 or 9 data bits
No, even or odd parity bit
1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of
nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits,
before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the com-
munication line can be set to an idle (high) state. Figure 20-4 on page 155 illustrates the possible combinations of
the frame formats. Bits inside brackets are optional.
Figure 20-4. Frame formats.
St
Start bit, always low
(n)
Data bits (0 to 8)
P
Parity bit. Can be odd or even
Sp
Stop bit, always high
IDLE
No transfers on the communication line (RxD or TxD). An IDLE line must be high
RxD / TxD
XCK
RxD / TxD
XCK
UCPOL = 0
UCPOL = 1
Sample
1
0
2
3
4
[5]
[6]
[7]
[8]
[P]
St
Sp1 [Sp2]
(St / IDLE)
(IDLE)
FRAME
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ83C154XXX-L16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MQ83C154CXXX-25/883R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MR80C154-L16/883R | 8-BIT, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ83C154CXXX-L16P883R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44 |
| MR83C154CXXX-20P883R | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQCC44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MQ80C154-20 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-25 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-30 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-36 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MQ80C154-L16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
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