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參數(shù)資料
| 型號： | MPE603ERX100LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | CERAMIC, BGA-255 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 135K |
| 代理商： | MPE603ERX100LX |
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EC603e Microprocessor Hardware Specifications (PID6)
25
1.8.2 PLL Power Supply Filtering
The AVdd power signal is provided on the PID6 to provide power to the clock generation phase-locked loop.
To ensure stability of the internal clock, the power supplied to the AVdd input signal should be ltered using
a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to the AVdd
pin to ensure it lters out as much noise as possible.
Figure 13. PLL Power Supply Filter Circuit
1.8.3 Decoupling Recommendations
Due to the PID6’s dynamic power management feature, large address and data buses, and high operating
frequencies, the PID6 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the PID6 system, and the PID6 itself requires a clean, tightly regulated source of power.
Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor at
each Vdd and OVdd pin of the PID6. It is also recommended that these decoupling capacitors receive their
power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize
inductance.
These capacitors should vary in value from 220 pF to 10
F to provide both high- and low-frequency
ltering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values
for the Vdd pins—220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the
OVdd pins—0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount
technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors—100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum).
1.8.4 Connection Recommendations
To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level.
Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND.
All NC (no-connect) signals must remain unconnected.
1.8.5 Pull-up Resistor Requirements
The PID6 requires high-resistive (weak: 10 K
) pull-up resistors on several control signals of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the PID6 or other bus master. These signals are—TS, ABB, DBB, ARTRY.
In addition, the PID6 has three open-drain style outputs that require pull-up resistors (weak or stronger:
4.7 K
–10 K) if they are used by the system. These signals are—APE, DPE, and CKSTP_OUT.
Vdd
AVdd
10
10 F
0
.1 F
GND
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